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We hope you get the i i interview! I have a significant gap in full-time employment. Thesis? I need to create a cover letter that can briefly explain that gap. The template of grow i i up want, a mother returning to work won’t cut it, IMO. Do you have a template that matches my needs? Thanks in advance #128578; We regret that you weren’t able to find what you were looking for. The stay at thesis on oceanarium home mom resume is one of our most popular and has received a lot of positive feedback.

We suggest that you check out our resume formats page: https://resumegenius.com/resume/resume-formats. You may want to consider using functional format to help cover up your work gaps. If you still need help, you may also want to consider signing for a subscription with us. We offer the regression analysis paper “Ask The Expert” service, which gives you access to a professional resume writer. Good luck on thesis, the job hunt! Hello I am applying for flight attendant position, but I have never worked in this position before. What title I need to put in the header of the resume? Our flight attendant sample has all the information you need to write your own resume. (https://resumegenius.com/resume/flight-attendant-resume-sample). Good luck on the job hunt!

I only have volunteer work how do I put that in a resume ? thanks you. Check out our “How to Write a Resume” writing guide. (https://resumegenius.com/how-to-write-a-resume) It should be helpful in answering your question. Very true and informative. Just googled it and no doubt remains now. Essay Grow Up Want When? Cover letter will be easy for me now. Glad you found our cover letter guide useful.

Let us know if you have any additional questions. Good luck on the job hunt! This was helpful. is it same for Student / Entry Level Cover Letter and Internship cover letter? We are glad you found our cover letter page useful. As far as your question goes, the student cover letter above could be reworked for an internship application. On Oceanarium? Please let us know if you have any other questions. This helped me so much, I’ve never written a cover letter before. Thank you so much RG! We are glad that the information is fmcg resume, helpful! Please feel free to read other related articles and let us know if you have any questions. Hey please i want to apply for a post of an armorer in the ministry of defense in our country advertised in the dailies.

It wants people with high school education and i basically have that. Please lead me through… We will need more information regarding the job posting as well as your background to lead you. Hi! Do you have cover letter samples to apply as a job intern? Not currently, but it is on our list of samples to thesis on oceanarium add.

For now, our student sample above should be helpful in giving you some ideas on how to format your own. Thanks a lot RG this was very helpful. Abeng Essays? Before today I have never done a one, now I have confidence with putting together a cover letter. One small question though, what should I name the thesis cover letter? We are glad that you found our cover letter resources helpful. You can simply name your it “Deitric (last name)’s Cover Letter.” That way, it will be easier for the employer to spot as they go through all the applicants in their inbox. Good luck on the job hunt! Hi!

I have never written a cover letter before and would like to thesis paper apply to a “work from home” job–but, have no idea how to write it. Please help! We have plenty of industry-specific samples above. On Oceanarium? Find your industry and get a few detailed tips on how to structure your own cover letter. RG I must say this helps me a lot. Abeng Essays? Not sure if I could master it but this would definitely help. Thank you so much for making my day 3. We are really glad to hear that and thank you for your support.

Please let us know if you have any question. I remain stumped as to how to address a cover letter in on oceanarium response to a job advertisement that gives neither the company name nor the name of the person in charge of hiring. This is true of many job postings on abeng essays, Craigslist, for example. I dislike “To Whom It May Concern”, but what other greeting would you recommend? Many job seekers also run into this issue.

When the posting doesn’t include a name of the company or hiring manager, try copying some of the job description and searching for it on on oceanarium, Google. Letter? You may find the on oceanarium job ad with the names included. Essay Grow I I Up Want When? If this doesn’t work, then it is acceptable to address the cover letter with “Dear Hiring Manager.” Good luck on the job hunt, I normally just put Dear Hiring Manager. I’ve had issues where you call and there are multiple people who do the hiring, so I don’t know who will be doing my interview until the thesis day I have my interview. If I ask the employee there like, “Oh I’m not sure.”

I’m going to forward this to essay when a client of mine I was just talking to him about this. Now he’ll know that I’m not just trying to make his life miserable. Great! We hope they find our resources helpful. I have done my resume and now I’m preparing myself to do CL, but I have problem with it, because everything is wrote in resume – especialy introduction. It would be the best if I could copy my introduction from resume to CL, because there is almost the same to write. please advise. Some of the contents from your resume intro should be used in you CL, but should not simply be copied. If you read the above guide and download the template pack, you will learn exactly what information should be included. Thesis? Also, be sure to check out our CL samples to give you a better idea on how you can word your cover letter.

Good luck on multiple regression analysis paper, the job hunt! I am trying to thesis write a cover letter for a managerial position in the hospitality field. However, I do not see any examples. We are in cover letter the process of adding new cover letter samples and have included your suggestion in the list. In the meantime, follow the guide above and download one of on oceanarium, cover letter templates. Good luck on the job hunt! Basically, a cover letter is a letter of term papers, introduction. Usually I state the name of the thesis on oceanarium position I’m applying for and why I am qualified for the position.

At the end of the letter, I’ll write something like “If you have any questions or to essay i i up want schedule an on oceanarium, appointment for an interview, please contact me at ***-**-****.” Then double space and type “Sincerely” and then space 4 times and type your name. You’ll be signing in the space above your typed name. This has been most helpful. GBU. Glad you liked it. Letter? Share it with you your friends. GBU, too! I am working on a resume for an experienced welder, One of the requirements is thesis, a valid drivers license, which I do not possess at this time , but if I was hired, I could pay the fmcg resume traffic fine and on oceanarium get my license back with my first paycheck. Should I explain this on my resume or by telephone or in person or not at mall. In all honesty, your best bet is to find a way to pay the effects warming papers traffic fine and get you license back before applying for the position. Thanks for the advice.

I was thinking that very thing or appearing at traffic court and setting up a payment plan which would clear the thesis way for a re issue. All about the money. Fmcg Resume? which I happen to be in on oceanarium short supply of. Thanks again. We know the struggle. Essay Grow? Hang in there brother! Try add figures that will impress an employer and on oceanarium that pertain to the position you are applying for. Best of luck! I live in Thailand and odd numbers here are auspicious so it probably won’t hurt to throw some of them in. I’m still not sure what you all are referring to with bullet point ‘numbers’. Can someone explain?

Thank you. thank you so much RG you really shade light on cover letters, i was clueless wat it was so mostly i would ignore it and send my applications without one from multiple regression analysis today i will do thngs differently. Download our cover letter template pack and on oceanarium use the tips written above. That should get you started. Best of of global, luck! How to address gaps in employment. My mom passed away unexpectedly in 2005. I was incapacitated by depression and unable to work from thesis 2005-2008. Got a job in 2008 was employed until 2012 when I had a baby. i have been a stay at effects of global warming term home mom. Ready to go back to work again.

How do I address the gaps when posting my resume on job resource sites? I have spent the past six months working reworking my resume. I’ve searched hundreds of thesis, resume websites; Resme Genius is, by analysis, far, the best. Would appreciate any advice. Thanks for the kind words. One of the easiest ways to mask your work gaps is to use a functional format: https://resumegenius.com/resume-formats/functional-samples-writing-guide. On Oceanarium? Give it a try and see what you think. Good luck on the job hunt!

How do explain a reason for grow i i up want when, leaving a company when you hate your job/employer, more management than the job itself. We always recommend not to burn any bridges with former employers and to leave on a positive note. Thesis On Oceanarium? So in that case, we suggest that you explain that you are looking for an opportunity in a new industry or a different position. Although it may sting, make sure to also thank management for regression, the opportunity you were given. On Oceanarium? Good luck! Struggling with how to address a cover letter for a summer internship. Multiple Regression Analysis Paper? I’m not applying for a posted internship, just going to show up at thesis an organization that my school advisor suggested I reach out to. I have no idea who I’ll be giving my cover letter to, but I don’t want to say “dear hiring manager” because technically they wouldn’t be hiring me… right?

Aside from that, this guide was still very helpful. We’re glad that you found our advice helpful. Letter Store? In your case, “Dear Hiring Manager” or “Dear Madam or Sir” would be appropriate. Good luck! So i have been asked to email my salary requirements, Here is my situation though, I previously worked with this company in the same exact role.

I left for on oceanarium, another job opportunity ( which built my skill set and experience) about a year ago this month. They have asked me to come back and fill that position again. Essay Grow? How do I compose a salary requirement. In this situation you have the leverage, so it would be fair to ask for 10-20% more than you were paid before. The skills and thesis experience you gained over the last year make you more valuable than you were before. Good luck!

Hi, I am trying to cover store help a friend who is looking to on oceanarium move into a completely different line of work, he has only had 1 job since high school, which has nothing to effects warming term do with what he really wants to do. How do you approach that in a cover letter, since he has no experience in on oceanarium the field? Your friend will have to discuss their general skills or traits that are relevant to the job. I just turned 62 and fmcg resume want to retire from my current job, but not ready to retire. Any suggestions on how to “put my best foot forward” when applying for a new position in thesis on oceanarium an industry I’ve never worked in before? When applying for a position in fmcg resume an industry that you’ve never worked in before, the first thing you should do is come up with a list of the relevant skills that you can transfer over to thesis on oceanarium that industry. From there, you can work on ‘selling’ those particular skills in your cover letter and store resume.

Good luck! So glad I stumbled upon this. Glad you found it helpful! I’m applying for on oceanarium, a new job but the mining company has different projects. Multiple Regression? Would I have the company’s address or the project site address? We recommend that you use the address that the cover letter is being sent to.

If you are not sure, then use the company’s address. Good luck! Some cover letter here have helped me move on to another level. Through this i had to pay bills for thesis on oceanarium, my ailing child . Thanks you have been of great help through the way to write a winning cover letter. Great information! My question is fmcg resume, I have been out thesis on oceanarium, of the work force for about a year and a half due to fmcg resume birthing children and staying home for them. I am wondering if this is something i should include on my CL to explain my gap in thesis on oceanarium work history or is this information to personal to include? Great question! If your work gap is letter, longer than a couple of months, then you should certainly include an thesis on oceanarium, explanation in your cover letter. Don’t spend more than 1-2 sentences on your explanation though. Remember that you want to fmcg resume keep the focus of your cover letter on thesis, your experience and qualifications.

You can say something like “After taking some time at store home with my family,” then express how excited and enthusiastic you are to return to thesis on oceanarium the work force and how this position is exactly what convinced you that now is the time to do so. You can use that phrase for grow up want when, maternity leave, or caring for older family members, or even your own issues. Shoot, you can use that even when you didn’t choose to take a break, so to speak. Good luck! I’m a college dropout and I couldn’t decide on which template to on oceanarium use for my cover letter. I quit school during my sophomore year. We suggest using the ‘Non-Student’ templates. If your college experience is abeng essays, relevant to on oceanarium the job you are applying for, you might consider including it your cover letter. Best of luck on the job hunt! Thank you Resume Genius!

what if there is no job description given? how do you start of with the multiple regression research paper cover application in thesis such a scenario? Even without a job description you can still follow the template above. Look up job descriptions for the same position from other companies to get an idea of what the employers is looking for. Unless requested in the job ad, leave your salary requirements off your cover letter. Thesis? Good Luck! Fair point – it’s always good to be careful when sending out personal information.

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TARGET COMPANY: START-UP IN EITHER TELECOMMUNICATIONS,SCIENTIFIC R D or MEDICAL EQUIPMENT R D. Company Size: Prefer small. Category: Electrical Engineering. TARGET LOCATIONS: Will Relocate with conditions. WORK STATUS: UNITED STATES I am authorized to work in this country for thesis on oceanarium any employer. Cover Letter Store? Have held Security Clearances.

Valid MASS Drivers License Class 3. Assigned tasks, maintained cost and schedule to a group of 20 Engineer and Manufacturing Personnel. Provided upper management monthly Progress Reports and thesis Weekly Departmental updates. Term Papers? Interacted with all required agencies, vendors, and customers to thesis meet corporate objectives and deadlines. Extensive expertise in quality, the Engineering Process. Highly skilled in Product Design Development of Electro-Mechanical Products. Participated in providing Technical Engineering Leadership and Support to System, Concept, Equipment, Readiness and Production Review in Transiting new Designs into a Solid Product. Developed and Documented Specifications, Concept Definitions, Analyses and Trade Studies of thesis, various Electro-Mechanical Systems. Highly Knowledgeable of CAD Systems in generation of Assembly Dwgs., Parts Lists, Detailed Dwgs. Altered Item Dwgs. Effects Term Papers? Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation, PWB Artwork, Mechanical Dwgs,as required.

Extensive hands-on experience in thesis on oceanarium, System Debug Component Level Troubleshooting, Electro-Mech Assembly, Integration Test, with wire-wrap and soldering expertise. Integration and grow up want when Test of on oceanarium, a variety of Computer Hardware. PROFESSIONAL WORK EXPERIENCE. SMARTWORKERS WAREHOUSE, Inc. Fitchburg, MA.

Assistant Store Manager/Customer Service Rep. Providing management assistance to Store Manager. Responsible for opening and closing. Assignment of multiple regression paper, daily retail task and scheduling of available manpower. Providing customers with benefits of thesis, my expertise in fmcg resume, the Art of Woodworking. Upgraded and thesis on oceanarium re-merchandise entire store increasing net sales by 30 . Have sold well over 250,000 woodworking tools in abeng essays, 8 months. MILLERVILLE PHOTO PROCESSING CAMERA, Inc. On Oceanarium? Millerville, MA. Photo Lab Technician/Customer Service Rep. Processing and developing all types of Photographic Media including Digital Photography. Handing of Customer questions and accountable for cash flow.

Expertise acquired in the service and multiple regression paper maintenance of Fuji Photo Processing Equipment. Generated documentation of all Photo Processing and Printing Procedures. Thesis On Oceanarium? Adhered to EPA Hazard Waste Requirements. COMPUTER AIDED SYSTEMS Boston MA. Consultant Electrical Engineer/Electronic Technician.

Provided WEB Based Engineering Design Services doing Schematic Capture and PWB Layouts of PLC Interfaces using OrCAD. Performed various Test Engineering activities. Involved in abeng essays, assessing and on oceanarium performing the overall Functional and In-Circuit Test activities in the production and essay grow i i repair of the thesis, DC-40 Handheld 486 Datacomputer w/LCD Display, PCMCIA I/F, Irda I/F, Modem I/F , and associated Power Supply SMD Assembly. Performed evaluation and refinement of a variety of Functional Test operations, debug analyses and cover recommended solutions to improve the production through-put and provide fully tested hardware to the customers of contract manufacturing firms. Created Final Test Procedure for the Nortel 1800 Chassis and thesis Modules Communication System Card PC603 Based, Modem Assembly w/SMD Modem Daughter Cards. Documented and Performed Functional Test Procedure for TELCO Communication PWB Modules, WATERS Corporation PWB Module and a variety of MKS Sensor SMD Assemblies. ADVANCED SYSTEMS CO., Pillsbury MA. Senior Development Engineer 1992-1998. Electronic Design Laboratory Lead Engineer and Cost Account Manager.

Provided upper management monthly Progress Reports and Weekly Departmental updates. Interacted with all required government customer agencies, Program Management Office, Manufacturing Engineering and other Design Laboratories to meet corporate objectives and deadlines. Thesis Quality Paper? Managed and thesis on oceanarium participated in abeng essays, Electrical Engineering involved in the specifying, designing, development, testing, debugging and qualifying prototype Electronic H/W. Responsible for the daily technical operation and security functions of the DoD Closed Area Digital Laboratory Central Test Facility. Upgraded and thesis on oceanarium maintained PATRIOT COMO Simulation Laboratory.

Technical Integration Lead to an engineering group of quality paper, 10 engineers, in both hardware and software. Incorporating, integrating and testing PATRIOT COMO I/II Telecommunication Upgrades supporting electronic assembly upgrades through Manufacturing and Depot Integration. Technical Lead Integration Test Engineer for the Radio Logic Routing Unit-Upgrade Integrated and tested a number of VMEbus designed Modules i.e.SBC, SIO, EPROM, ethernet supporting the RLRU-U transition to production and on through qualification testing at Field Sites. Technical Lead Electrical Engineer for PATRIOT COMO UPGRADES participated and provided input to System, Concept, Equipment, Readiness and Production Reviews. Assistant Subcontract Manager for Smart Matrix Unit GTE and Lightweight Computer Unit SAIC integrated, tested and qualified into PATRIOT COMO. Development Engineer 1990-1992. Electronic Design Laboratory Lead Engineer and Cost Account Manager for TACIT Rainbow Mission Computer TRMC . The TRMC is based upon a MC68030 with dual MC68332s along with two subsystems interface modules and a power supply. Supervised and directed four Electrical Designers. Participated and provided Technical Engineering Support to System, Concept, Equipment, Readiness and Production Reviews transiting the TRMC Design into a solid Product with the help of Concurrent Manufacturing Engineering. Developed requirement Specifications, Concept definitions, analyses and performance trade-offs of various system architectures. Generated Assembly Dwgs., Parts List, Detail Dwgs., Altered Item Dwgs., Component Spec/Source Dwgs., Electrical Schematics, Interface I/O Documentation,PWB Artwork, PWB Mechanical Dwgs. as required.

Built, Serviced and Maintained the TACIT RAINBOW Software Development Facility, integrated prototype H/W along, with SPARC Workstations, IBM-PCs and Silicon Graphics Workstations in thesis, the performance of software code development, system simulation and software performance evaluations. TRMC 80 Logic in Altera FPGAs No PWB Design Errors. Directed Multiple Laboratory and multiple regression research Manufacturing resources into developing a fully integrated, form-factored and tested unit which was integrated into the TACIT RAINBOW Missile Prototype and Tested using LABVIEW. Senior Electrical Engineer 1987-1990. Digital Design Laboratory Lead Engineer and Cost Account Manager. Provided upper management monthly progress reports and weekly departmental updates.

Assigned design tasks and maintained cost and schedule. Lead Engineer for MIL-STD-1760 Missile Simulator Unit MSU 68020 based simulated aircraft stores interface for F15/F16/F18. Provided User Interface ports Monitor, Serial and Parallel Printer interfaces. Thesis? Tested and thesis paper qualified to MIL-STD-810C 12 units. Lead Engineer for Missile Integration Test Set MITS Integrated, incorporated and tested Short Round Test Set into MITS H/W to provided Full-Up Missile Test. Lead Engineer for thesis Dynamic Software Test Facility DSTF for software development designed, developed, integrated and tested a facility based upon five MC68020s, simulated internal missile interfaces via specialization circuitry and utilization of Personal Computers. Electrical Engineer 1986-1987.

Module Design Engineer responsible for all components of the multiple regression paper, Module Design Process. Coordinated and supplied technical design input, integration test and on oceanarium operational inputs for of global innovative subsystem development. Redesigned the Digital Signal Processor and upgraded Missile H/W turning TTL Logic into Gate Array Logic using reverse engineering techniques. Designed and Supported two Missile PWBs using MENTOR, one a Data Acquisition Module 25 Analog/75 Digital and the other a Aircraft HOW Interface Module 50 Analog as part of Low Cost Seeker Program HARM. Engineering Specialist 1985-1986 Specializing in Motorola Microprocessors incorporation, integration testing. Designer for Drop Test Seeker DTS Program Zilog Z8002 based Integrated Custom 10K Gate Arrays with Micro-Wire Technology using MENTOR and thesis on oceanarium VHDL PWB Designer of Pre-Amplifier Module 100 Analog using PSPICE and MENTOR Proposal Engineer for US Navy Outer Air Battle Program. RADMEX Inc. Boston MA. Senior Electronic Design Engineer.

Performed and Specified the effects term, Electrical Design, Electronic Circuit Prototyping, PWB Layout, Product Documentation, H/W Development, Integration and thesis Testing of a Computerized Newspaper Pagination System for a start-up company. Product Line developed and marketed was the Breeze Workstation , BitCaster Data Controller , BitPrinter Printer , BitSetter Typesetter and BitPlater Laser Platemaker . Warming Term? Involved in all phases of electronic and product design, S/W H/W integration, test, production implementation, field service and marketing. Design/Developed a Raster Image Processor based upon thesis, the AMD2903 Bit-slice processor form factored on of global warming term papers, a 12 x 12 multi-layer PWB using inverse euro-connectors. Designed/Developed a Micro-Controller AM2910 with extensive memory, which produced a 96-bit microword form-factored on on oceanarium, a 12 x 12 multi-layer PWB. Essay When? Developed unique high-speed clock using PAL Logic. Thesis On Oceanarium? Used Future Net and Multi-wire prototyping. Designed/Developed a Dual Port Module on a two-sided PWB using light table, which allowed the i ncorporation of a wide range of Off-the-Shelf Multibus I Modules.

DAYNEON COMPANY, Bedford MA. Test Engineering Aide. Worked in the Missile Integration and Test Department of the Missile Guidance Laboratory while attending NU. Assisted in the integration and testing of the prototype AMRRAM Missile. Involved in the development of cover, a Missile Readiness Test Set MRTS . Thesis? Responsibilities included: Creation of overall MRTS System Level Diagrams; Generation of Schematics, Part List and Wire Lists; Assembly Drawings.

Oversaw building of unit and performed engineering inspections;Performed initial testing and qualification testing. PANAMETRICS Inc., Waltham MA. Design Engineering Aide. Under direction of abeng essays, Physicist and thesis on oceanarium Electrical Engineers worked as a member of the Radiation Physics Laboratory while attending NU. Performed tasks in i i up want when, Prototyping, Development and Testing of various, Satellite Subsystem H/W for GOES Program. Held various jobs while attending college. Thesis On Oceanarium? Worked as Security Guards, Cashier at Store24, Retail Sales at Building 19 3/4, Bottling Production Line, Electro-Plating Operator, and Warehouse Laborer. Had own summertime Painting and Landscape Business. 1981 NORTHEASTERN UNIVERSITY US-MA-BOSTON.

Bachelor s Degree BS ENGINEERING TECHNOLOGY. 1976 Sylvania Technical School US-MA-Waltham. Certification COMPUTER ELECTRONICS. 1974 UNIVERSITY OF MASS US-MA AMHERST. Courses PSYCHOLOGY/CRIMINAL JUSTICE. ELECTRICAL ENGINEER/TECHNICIAN with extensive hands-on experience in SYSTEM DEBUG COMPONENT LEVEL TROUBLESHOOTING, ELECTRO-MECH ASSEMBLY, with WIRE-WRAP AND SOLDERING EXPERTISE.

Expertise with Microprocessor/DSP/Embedded Designs AMD, Motorola, Intel, TI ;Analog Design, RF Design, High Speed Digital Circuit Design; FPGA/PAL Logic Xilinx, Altera, Actel ; VHDL; Multilayer PWBs and SMD Assembly, EMI Design Techniques, Backplane Design Multibus I/II, VMEBus, ISA, PCI Bus Serial I/F: RS423, RS232C, RS422, RS485 PARALLEL I/F; 1553B I/F, IEEE-488; LCD Displays,PCMCIA I/F, Irda I/F, Modem I/F, SCSI1/2/3 I/F; Ethernet, Fiber I/F; Optics, Integration of a variety of computer hardware; Familiarity with Test Equip./ATE. PROJECTS, WORD, EXCEL, POWERPOINT, MENTOR Schematic Capture/Logic Simulation, PSPICE, CLARIS DRAW, MENTOR PWB LAYOUT, OrCAD,WINDOWS w/LABVIEW, MATHLAB; Assembly C Programming. DIGITAL TECHNOLOGIES, San Jose, CA. Involved in cover store, Ethernet/firewall product development for the OEM customer base. Designed the architecture for the current ASIC Ethernet hub/switch. Thesis? This SOC included an ARM 7 processor, 5 MACs, a Triple DES core and 24K of Dual Port SSRAM using .25-micron technology.

Headed the design team in the implementation of the chip. VHDL was used for the design implementation. Effects Of Global Warming Papers? Designed the on oceanarium, board level firewall product that uses this ASIC. Implemented a Triple DES core into an Actel FPGA that was used on the low-end firewall product line. Designed a three-channel Fast Ethernet firewall controller using an store, Intel ARM 9 processor and on oceanarium an ITE PCI bridge. In charge of engineering development of board level designs for both product and OEM reference. Additional engineering responsibilities include: Wrote specifications for both chip and board level products. Wrote guidelines for PCB layout that encompasses component placement for high-speed signals and FCC compliance testing.

Incorporated manufacturability into designs including ATE. Developed and maintained project schedules. Interfaced with the software department for BIOS and POS functionality. MIRRENFAX IMAGE PRODUCTS, Sacramento, CA. December, 1997 to February, 1999.

MANAGER OF ENGINEERING. Manager of the hardware engineering team. Involved in product planning for a new family of of global term, OEM image processing controllers. These controllers are installed in thesis, high-end scanners and multiple paper allow Virtual Rescanning while automatically changing the on oceanarium, image characteristics deskew, thresholding, intensity, cropping, etc. . Fmcg Resume? Responsibilities include interfacing with scanner manufactures during product definition, scheduling of product development, resource management, project management, ASIC vendor selection and CAD tool evaluation and purchasing decisions. Involved with defining the next generation Image Processing ASIC. Responsibilities included defining functionality, project management, and thesis vendor coordination.

Also, designed the system architecture for a second ASIC that became the system intelligence. This contained an fmcg resume, embedded ARM7 processor, PCI interface, DRAM, etc. Led the design efforts on this second ASIC. Both ASICs were in the 1M to 1.5 M gate range and implemented in thesis on oceanarium, .25-micron technology. VHDL was used for the design implementation. Designed several controller boards that used these ASICs for fmcg resume different scanners. CMD TECHNOLOGY, Sacramento, CA. June, 1995 to December, 1997. MANAGER OF ENGINEERING. Managed the thesis on oceanarium, Raid Division engineering team.

Responsibilities included scheduling, budgeting and product development for both board and system level Raid products. Involved in defining the next generation architecture of Raid controllers that was comprised of multiple analysis research paper, a four ASIC chip set. Project Manager for a Digital Equipment Corp. On Oceanarium? specific Raid controller. This project was a joint effort between CMD and fmcg resume Digital with CMD designing the controller and Digital doing the mechanical packaging. Thesis On Oceanarium? Responsibilities included coordinating the hardware efforts between the cover letter, two companies along with designing a FPGA that interfaces to thesis on oceanarium Digital s EMU and Fault Bus. Designed the Raid controller board that was used by Digital. Designed several other Raid controller boards that were used for the OEM market. Member of the Change Control Board CCB and the Advanced Products Group. Involved in abeng essays, implementing procedures between Document Control and Engineering.

CORSER CORP., Costa Brava, CA. May, 1992 to June, 1995. Involved in the design of thesis, a DAT tape controller ASIC which interfaced to a SP1 format tape drive. This ASIC was implemented in .8-micron technology. Designed the next generation DAT tape controller ASIC. This chip was implemented in .6-micron technology and has approximately 80K gates.

Designed the tape controller board that uses the new ASIC along with a Data Compression/SCSI ASIC, V50 microprocessor, 1 MB of DRAM buffering and FLASH EEPROM. Joined the Arcuate Scan Tape group and designed an ASIC used in controlling the tape head preamps. This ASIC was mounted to the head assembly using chip-on-board technology. Also designed the Servo Gate detection ASIC used for head positioning. All ASICs designed and letter store simulated at Conner were done using VHDL.

IRVEL CORPORATION, Scottsdale, Arizona. December, 1988 to April, 1992. MANAGER OF ENGINEERING. Management responsibilities for engineering, software, and test departments. Established procedures in thesis on oceanarium, top-down design methodology and functional specifications for the Software and essay i i up want Hardware Departments. This provided a path for designs with a high degree of modularity and ease of software/hardware integration. Defined future products and initial marketing strategies. Designed a proprietary Error Detection and Correction ASIC to be used in memory intensive products. A 16 and 32 bit version of this ASIC was designed in 1-micron technology and consisted of 34K gates.

CAD tools used in these ASIC designs include Cadence for thesis schematic capture and Verilog for simulation. Also designed a PC compatible memory board that incorporated this ASIC. Developed specifications, in conjunction with IBM Boca Raton, Florida , for a high performance PS/2 memory board. Involved in setting up incoming test procedures for partial memories using a Teradyne tester. Fmcg Resume? Two patents emerged from the research of memory subsystems. FUTURAMA, Sacramento, CA. October, 1984 to November, 1988. PROJECT MANAGER/SENIOR ENGINEER. Involved in writing product specifications for on oceanarium an advanced system architecture that was incorporated into a microprocessor development system. Interfaced with the software development group to identify areas of concern when porting UNIX on abeng essays, to the new system. Designed a 68000 based CPU board for on oceanarium this development system.

During the design phase of the CPU, research was done on interfacing a 68000 to various memory management techniques along with different bus structures Multibus, IEEE 896, and abeng essays VME . Designed the system protocol that provided an efficient means of on oceanarium, communication between the CPU and intelligent, DMA driven, I/O controllers. Designed an intelligent SCSI controller that used this protocol. TRIANON CORPORATION, Sacramento, CA. March, 1981 to October, 1984. PROJECT MANAGER/SENIOR ENGINEER.

Project Manager for the Mark III minicomputer. Responsibilities included managing an engineering team and coordinating the software and thesis paper manufacturing departments efforts on the project. Designed the hardware and firmware for the Mark III Peripheral Interface Board that contained a tape streamer interface, four asynchronous ports and a two-port SMD/CMD disc drive interface. The Peripheral Interface Board was designed using discrete logic and incorporated the thesis, 2903 bit slice architecture for the micro-engine. The firmware consisted of 32 bit-wide microcode. COMPUTER AUTOMATION, Sacramento, CA. June, 1977 to March, 1981. Engineering team member involved in the development of a new processor and the related I/O controllers.

Designed the cover letter, interface protocol and an I/O relay controller for this processor. This team was located in Dallas, Texas. Previously: Designed a debug module including hardware and firmware that could be used for debugging Z80 software. There was also a 32-channel trace for storing address, control, and data lines upon receiving a pre or post trigger. The back-end contained the necessary handshaking to thesis a modem so the board may be used remotely from the multiple regression analysis paper, operator. Initial assignments upon joining the company involved sustaining engineering hardware and firmware for a disc drive controller, synchronous communications controller, MOS memory board and static problems with CRT s. BSEE, California Polytechnic University, San Luis Obispo, California, 1977.

Concentration in Computer Systems. Will be furnished on request. Six years of strong experience in research, analysis, design, development of instruments using VHDL/VERILOG, ASIC Design, FPGA design, digital design techniques, design using microprocessors and micro controllers. Expertise in design and simulation of electronic circuit boards using orcad, spice, circuit maker and thesis on oceanarium smart work. Expertize on regression analysis paper, Active HDL simulation package. Languages: C, C++ Application: FPGA, ASIC design, PCB design, Digital and analog circuit design Tools: Xilinx, Xilinx FPGAs xilinx 4000XL series, XILINX VIRTEX series , Cypress. Thesis? Hardware Definition Language HDL : Verilog, VHDL, 8051 assembly HDL Tools: ModelSim VHDL, Leonardo Spectrum, RAD51 assembler, ORCAD, Spice.

Compiler: AVC51 Operating System: Unix, Windows NT/95/98. Digital Automatic Moisture Computer. September 2001 - Till date. Development of a stand alone device to abeng essays measure moisture content of various agricultural products. Thesis? Involved in multiple paper, Design and development of automatic moisture meter both independent and computer interfacable.

First prototype developed around 8051 microcontroller using AVC 51 for thesis embedded system. Multiple Research? Involved in sensor design. Design and coded same using C. Handled design and fabrication of analog and digital boards for thesis on oceanarium first prototype. Second prototype being developed as full custom SOC System on chip for thesis paper the calibration circuit around microcontroller 8051using simulation and on oceanarium synthesis tools of mentor graphics. The input taken by abeng essays, sensor directly displayed in thesis, terms of percentage moisture. Development of calibration technique based on method of least squares. Writing source code and test benches in VHDL for interfacing of store, 64K RAM, ROM, decoder and their interfacing with the A/D converter and PGA. Simulation of calibration process and verification of functionality and timing errors for same. Synthesizing code on Xilinx virtex series using Xilinx FPGA.

Environment: RAD51 assembler, AVC51, Mentor graphics, VHDL, Modelsim and Leonardo Spectrum, Xilinx, Virtex, Windows NT. Central Scientific Instruments Organization. 8 BIT Microcontroller ASIC Design Engineer. Involved in on oceanarium, design of effects of global warming, a 8-bit micro-controller having features of thesis, INTEL 8051 microcontroller. The FPGA consists of 128K RAM and 64k ROM and is instruction compatible to the Intel 8051.Prepared library package for the instruction set of the microcontroller in VHDL. Wrote source code for the ALU to perform various arithemetic and logical opeartions. Warming Papers? Source code for the RAM and ROM entity was written and debugged using test bench generation schemes. A complete model of the FPGA was designed using the above logical blocks and thesis on oceanarium the design was implemented on Xilinx VIRTEX FPGA. Letter? a memory mapped output port was also added to the design. Environment: VHDL, Intel 8051 training kit, mentor graphics software , synopsys , Xilinx tools. Central Scientific Instruments Organization.

Microwave Oven ASIC Verification Engineer. Involved in the design of high frequency switching circuit to thesis operate at 2.5 GHZ using spice simulation software.Involed in counter design for abeng essays the programmable counter for the magnetron switching circuit. Involved in debugging, verification and analysis of on oceanarium, critical timing parameters for low power consumption and area size using Mentor graphics Leonardo spectrum synthesis tool . Synthesized circuit around rtl resistor transfer level after calculating timing delays and critical path parameters. Environment: Spice simulation software for mixed mode signals, Mentor graphics simualtion and synthesis tools. Department of Science and Technology DST. Video Chip simulation ASIC Verification engineer. A VMIS Video million images per second embedded processor was studied and was simulated for warming term various digital applications. Captured top-level video inputs simulation of VMIS video million images per second TV controller chip having an embedded processor. Thesis? Enabled signal processing for digital applications. Worked in a team for simulation of chip. Carried out chip verification using using tools from mentor graphics.

Verified ASIC for rtl resistor transfer logic syntax and semantics. Used Configuration Management Tool for database version control. Environment: Embedded processor from sigma Electronics, Mentor graphics tools, VHDL, Windows 98. Technology mission for oil seeds and pulses. Sept 1998- June 1999. NIR Near Infra red BASED CEREAL / GRAIN ANALYSER Hardware engineer. Selected photodiodes according to wavelength of various samples to letter be measured for different parameters.

The selection of thesis on oceanarium, photodiodes was done to fmcg resume opearte at radio frequencies. Designed analog and digital board around SPICE simulation software. Interfaced memory and display using embedded system programming using AVC 51, RAD 51 around microcontroller 8051. Further, an FPGA was developed to perform the application of microcontroller 8051 and the entire calibration circuit was interfaced around the Xilinx FPGA. Coded using VERILOG. Thesis On Oceanarium? The digital circuit associated with ROM, RAM, decoder,latch was implemented with the letter, developed Xilinx FPGA microcontroller . As a team member wrote source code for the FPGA microcontroller features and tested the functionality of interfacing circuit and simulated it using modelsim VERILOG. Environment: Microcontroller 8051, AVC51 and RAD51, Spice, Mentor graphics tools, model sim, Leonardo spectrum, Unix shell scripts. Department of Science and Technology DST. CPU Central Processing Unit Design ASIC Design Engineer.

Designed and developed a 8-bit microprocessor. The device consists of a RAM, ROM, a high speed ALU, shifting, decoding and multiplexing circuitry. Made package for the instruction set of 8085 in VHDL. Wrote source code for the ALU to thesis on oceanarium perform arithmetic and logical operations using VHDL, source code for the RAM and ROM implementation. Simulation of the regression analysis paper, functionality of the processor using test benches on thesis, Active HDL simulation package in Window NT environment. synthesized the same on XILINX FPGA. Environment: Active HDL, Vinytics 8085 microprocessor kit, Xiilinx spartan series,Windows NT. Technology Mission of Oil seeds and Pulses. Digital aflatoxin meter Test Engineer.

Designed electronics related to analysis research system around ORCAD IV , checked for the functionality of the design using mixed mode signal simulation around ORCAD IV and development of calibration software around microprocessor 8085. Documented instrument for transfer of know how and providing intensive training to user on how to use same. Environment: ORCAD IV, Vinytics 8085 kit, assembly programming for 8085. Department of science and technology. Sept 1996- March 1997. Gold Analyzers Test Engineer. Developed analog and digital electronics design circuit board using ORCAD.

Checked the functionality of the same and thesis on oceanarium its interfacing with the sensor. Documentation of instrument. Involved in selection of principle of purity measure using non-destructive technique based on energy dispersive X-Ray fluorescence spectrometry. Environment: ORCAD Version 1V, Windows 98. The projects around VHDL were coded and tested before synthesis and also associated with PAL Programming, analog and breadboard testing. Store? Responsible for integration and on oceanarium test of a UART, real time clock, keyboard controller, DMA controller and interrupt controller chip. This helped in abeng essays, gaining good understanding of ASIC design and verification methodologies along with PAL and FPGA programming. Thesis? Responsible for working with clients on intensive short term methodology training.

Responsible for quality paper training students in thesis, VHDL, synthesis and methodology. Aid in adaptation of training materials and development of new training classes. Paper publications and fmcg resume presentations have been made on Digital Automatic Moisture Computer and Capacitive moisture measurement of thesis, grains and oil seedsin various national journals. Training has been imparted to thesis quality paper various engineers and students of engineering colleges from thesis on oceanarium time to time. Significant contribution in organization of various seminars and conferences related to paper instruments developed, various projects for water quality monitoring and thesis soil analysis have also been designed and developed. B.S. in Electronics Engineering. Assume a role in ASIC Verification/Applications/Design Engineering. 4+ years experience in the EDA Verification Industry.

Senior Project Engineer (Promoted from Applications Engineer) Technical Lead for a TtME (Time to Market Engineering - a design verification consulting service) project for a Germany based company. Successful completion of the project lead to the sale of an essay i i, emulation system. Verified a 2+ million gate ASIC design. Assisted in project startup, Assessed project needs for verification and implemented design optimizations (for environment, RTL level and thesis on oceanarium simulation). Executed project milestones such as running RTL design (Verilog and VHDL) through synthesis and simulation, providing training implementing Cadence verification tools on site. Used test benches for passing vectors and debugging simulation differences.

Implemented Verification Flow. Regression? Identified introduced Cadence tools to the Verification process. Advised on design methodology and validated the subsequent setup. Lead Engineer for a European account (Philips - HDTV division): Consulted on thesis, Verification flow, and provided optimization ideas. Offered on multiple regression analysis research paper, site support and tool integration. Implemented a synthesizable cycle based design and test bench, and helped with the execution. Assisted in customer evaluation (San Jose based IC design company for DTVs) for a simulation acceleration beta product.

Worked with verification engineers to write optimized test benches. Worked on a product evaluation with Ericsson, Sweden, that resulted in sales for thesis on oceanarium numerous simulation software licenses. Worked closely with Quickturn RD and a third party RD (Verisity) that provided the testbench generating tool. The customer desired a combined product of 3 verification products along with a testbench generating tool. Research? Worked with QT and thesis Verisity s RD to integrate all of these products. Provided post-sales technical support and worked to increase the simulation performance. Used profiling tools to determine simulation speed bottlenecks. Implemented RTL and C model design changes for maximum performance optimizations. Successfully completed a TtME project with Ericsson, Germany, over a four-month period. This involved remodeling (in Verilog) significant portions of their design, testbench and memory models to be cycle based. Debugged differences in simulation results between Speedsim and the customer s internal simulator.

Successfully completed a two-month TtME project with Cabletron. Support included consulting on testbench methodologies, creating a synthesizable testbench, remodeling LSI memories to be cycle based, and making the LogicVision environment compatible to Speedsim. Fmcg Resume? Assisted the thesis, Quickturn India Distributor with a customer evaluation. Responsibilities included going on site and using test bench methods, passing vectors for showing proof of Speedsim functionality and grow i i up want performance on their design. Provided training to Application Engineers on topics related to simulation/acceleration tools during boot camps and other training sessions. Worked on thesis on oceanarium, numerous customer benchmarks which required verifying 1+ million gate ASICs with Quickturn/Cadence lint checker, synthesis, simulation, acceleration and thesis quality emulation tools. Presented demos and presentations at DAC 98 and thesis DAC 00. Corporate Technical Support Specialist:

Provided technical support for all of Quickturn s Simulation/Acceleration products. Clients included Ericsson, Intel, IBM, Lucent, AMD, Fujitsu, Philips and Mitsubishi. Multiple Regression Analysis Research? Played a product specialist role, with responsibilities including: Supporting Customers Quickturn Application Engineers: coordinating and resolving software, hardware and design related issues, problems, bugs and thesis on oceanarium questions. Providing workarounds to customer issues and working with RD to get critical customer bugs fixed as soon as possible. Was hired as ASD s (advanced simulation division of Quickturn) very first technical support specialist for Speedsim. ATRA Corp., Bayer Inc. Co-Op Internship (full time) Modeled a MC68HC11E9 Microcontoller Unit in store, VHDL.

The unit included microprocessor and memory components. Implemented design and verification with the help of ViewLogic tools like ViewDraw, ViewSim and ViewTrace. M.S, Electrical Engineering, University of Massachusetts, Lowell, MA Dec 96. B.S., Electrical Engineering, Regional Engineering College (REC) Surat, India Aug 94. Expertise in Cadence Simulation, Acceleration and Synthesis Tools. Experienced with ViewLogic Schematic, Design and Waveform Viewer tools. Simulation software: Powersuite, Speedsim, Megasim, PowersuiteVHDL, SPICE Emulation/Simulation Acceleration Cobalt, Radium, Palladium DAI: SignalScan, CompareScan Novas: Debussy Mentor Graphics: MTI View Logic: ViewDraw, ViewSim and ViewTrace.

Strong Verilog skills, VHDL, C, Unix, Perl. References available on request. ASIC PHYSICAL DESIGN ENGINEER. To achieve excellence, to be resourceful and on oceanarium optimistic and to abeng essays pursue a challenging career in thesis on oceanarium, VLSI design. Area of specialisation : ASIC Design Flow and abeng essays Methodology, Simulation, Synthesis, Floor plan, Place Route, Timing Verification, CTS. Summary in short : Have got more than 20 months of experience in the field of VLSI. Worked in logical design for 8 months rest in physical design. Moreover i have done my academic project in VLSI field. Arsanti!

Software Development Center(I) Pvt Ltd. Design Service Engineer(Physical design) Creating various test cases Benchmarks for customers. Used to thesis create testcases for analysis paper QA of Avanti tools. Creating testcases to thesis on oceanarium check various releases of Avanti tools. Cover Letter Store? Clearing Customers doubts queries regarding design tools. Vdesign Training development Centre Pvt lt. Trainee Design Engineer.

Responsiblities : Logical design Digital design. Thesis? Writing Verilog codes for various small Designs. Writing Test benches for letter store designs. On Oceanarium? Writing Scripts to check the designs. Undergone training on FPGA/ASIC design flow(logical design) and store methodology,HDL coding for circuit implementation and test bench,simulation, timing Verification,Floorplanning,Place Rout (Vdesign Training Development Centre, PondyCherry). Undergone training on on oceanarium, ASIC design flow(Physical design), Datapreparation, Floorplan,Place Route,timing, Physical Verification(DRC LVS). (Time To Market Ltd, Secunderabad). Projects carried out: (Physical Design) Design Specification: Hierarchical design with 5 softmacros. Hierarchial Floorplanning of Top Cell with core utilization of 75%, alongwith floorplanning of fmcg resume, each soft macros with utilization of 80%. Thesis On Oceanarium? (Tool used Planet PL ApolloII) Timing Driven Placement of each soft macro with constraints from Synopsis Design Constraints(SDC). (Tool used ApolloII Saturn) Clock Tree Synthesis (CTS) of eachsoft macro with a target of skew of research paper, 0.2ns and phase delay 0f 2ns.

The CTS is carried out for the Top Cell also. On Oceanarium? (Tool used ApolloII). Routing of abeng essays, each macro and on oceanarium the Top Cell. (Tool used ApolloII). Physical Verification for DRC LVS for each macro and the Top Cell. (Tool used Hercules). Company : TTM( as a part of training program in Physical Design) Designing of Standard Cells of 0.24 technology along with DRC LVS check. (Tool used Enterprise Hercules) Die Reduction Power Analysis : With a core utilization of essay i i, 98.5%. Contains 19 hard macros, and 28k standard cells. (Tool used ApolloII Mars-Rail) Timing driven :Flat design with an initial slack of -61.3, and congestion overflow of 4.03%. (Tool used ApolloII Saturn)

BenchMark For LSI logic involving diesize with 30k std cells with core utilization of 96%. Thesis? BenchMark For LSI logic involving Congestion driven placement with a core size of 26,000,000 micro^2. Bench Mark for Teralogic involving timing with Tristate Nets High Fanout Nets with timing specs difficult to meet. Bench Mark for Teralogic involving Design Planning starting from synthesis to Global rout Its mearly an abeng essays, analysis. (Tools used for above BM's: Apollo, Saturn, MilkyWay, JupiterP) EIGHT-BIT MICRO CONTROLLER. DESCRIPTION: The microcontroller which is the true computer on thesis on oceanarium, chip.The design incorporates all of the features found in a microprocessor ie. CPU,ALU,SP,PC,genaral purpose registers and special purpose registers.It also has added the other features needed to make a complete computer ie.ROM, RAM, parallel port, serial port, counter and clk circuits Like microprocessor , microcontroller is a general purpose device but one that is meant to read data, perform limited calculation on of global warming, that data and controls its environment based on these calculation. TEAM SIZE : 7 members. DURATION : 3 months. MY PARTS : CPU, counter timers, Interrupts, ROM and thesis RAM.

POLARIS for simulation. EXPLORERTL for RTL analysis. RTL MODEL OF FOUR BIT MICROPROCESSOR : DESCRIPTION: This four bit processor consists of the following components such as multiplexer, program counter,register,instruction decoder,ALU and timimg control,RAM and ROM .RTL code and testbench had been written for all the above units.Various stimuli had been given and papers the logic had been validated. TOOLS USED : simulator : MODEL SIM PE 5.3b. DURATION : JAN-2000 to APR-2000. COMPANY : Vdesign, Pondycherry.

10th Matriculation 1993 -1994 74% Higher Secondary 1994 -1996 81% B E in Electronics and Communication 1996 -2000 70% (Affiliated to Madurai Kamaraj University, TamilNadu). Hardware languages : Verilog. ASIC Methodologies : RTL and Behavioural. Assembly languages : Microcontroller. Software languages : C. Operating Systems : Unix,Windows. Script Language : Perl, Unix Shell Scripts, Scheme Scripts(Especially Avanti's Scheme), AWK, SED. Time Conscious. A go-getter. Quest for perfection in thesis on oceanarium, all assignments. Date of of global warming term papers, Birth : 02-08-1977.

Language Known : Tamil, English. Nationality : Indian. Marital Status : Single. References : will be provided on thesis on oceanarium, request. Three years of strong experience in VLSI/ASIC/FPGA design using Verilog HDL, VHDL, VERA HVL, VI editor, VIM, ModelSim, Xilinx FPGA Foundation series, Turbo C, SignalScan, Advanced Norton Editor, Synopsis DC, Cadence Artist, SPICE, SimG, ADSP2115 toolkit, EPROM/EEPROM programmer under Windows NT/95, UNIX and Sun Solaris environment. Digital Logic Design VLSI/ASIC/FPGA Design ASIC/FPGA Verification EDA Tools Simulation and Synthesis tools Design verification using VERA HVL. Hardware Description Language: VHDL, Verilog Design Tools: Modelsim, VCS, SPICE (TI-SPICE), ADSP 2115 toolkit Verification Tools: VERA Hardware Verification Language (HVL) EDA Tools: Synopsis Design Compiler, Xilinx FPGA Foundation series, Cadence artist Protocols and Standards: Digital wrapper (ITU-T G.709 standard) for FEC in 10GWANPHY, SONET OC-3/3c and OC-192, PCI Bus Interface, ATM, Ethernet, Transition Minimized Differential Signalling (TMDS) for Flat Panel LCD Monitors Languages: C, C++, PERL Operating System: Sun Solaris 2.1, Windows NT/98/95, Unix, MS-DOS Hardware: 10GWANPHY optical board, HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205), MPC8260. March 2001 - Till date. Digital Wrapper FEC (ITU-T G.709) Optical Channel Overhead Processor FPGA for 10GWAN.

Developed 10GWANPHY (10Gbps WAN) optical board which provided a complete switching fabric solution for Optical Wide Area Networks to support OC-192 Digital wrapper transmission standards (as defined by ITU-T G.709). Developed architecture and coded Transport OverHead (TOH) FPGA which interfaced with HUDSON FEC (AMCC S19203), KHATANGA (AMCC S19205) devices and effects of global warming term MPC8260 Motorola Power PC via its Local Bus. HUDSON is fully integrated with Variable Rate Digital Wrapper Frammer/Deframmer, Performance monitor and Forward Error Correction (FEC) device developed by Advanced MicroCircuits Corporation (AMCC). KHATANGA is a dense VLSI device developed by Advanced MicroCircuits Corporation (AMCC) that integrated a 10GbE MAC, a 64B/66B Physical Coding Sublayer (PCS) and thesis on oceanarium a WAN Interface Sublayer (WIS) as baselined by IEEE P802.3ae task force. Used this FPGA to configure HUDSON through its microprocessor interface port, control and fmcg resume monitor status of Optical Channel Overhead bytes/Sonet Overhead bytes (Transport overhead and Section overhead of OC-192c frame) in data channels of HUDSON and to support all Insert/Drop Overhead Channels of HUDSON and KHATANGA.

Defined 16-bit Register Memory Map inside this FPGA with predefined memory locations for Parallel 8-bit Overhead Insert/Drop channels of HUDSON (both Encoder and Decoder sides) and for serial Insert/drop Channels of Hudson and thesis KHATANGA. MPC8260 wrote overhead byte information into FPGA memory locations defined for those particular interfaces, which will later be inserted into insert channels on the next frame. On Drop channels FPGA collected Overhead byte information and stored them in internal predefined memory locations that will be later read by MPC8260. FPGA also monitored all status pins of effects of global warming term, HUDSON device like Loss of Clock, Out of Frame, Bit Parity Errors (BIP) and reported them to MPC8260. Thesis? Implemented FPGA on Xilinx Virtex XCV200E series (FG456 package) and implemented all dual port RAMs using 28 Block RAMs available inside this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of the abeng essays, chip.

Automated critical parts of design verification using VERA HVL. Coded MPC8260 local bus, HUDSON and KHATANGA interface modules in Verilog HDL using VI Improved Editor (Vim). Simulated functionality using ModelSim (Modeltech_5.5). Involved in synthesis of modules using Xilinx FPGA tool. Environment: Verilog HDL, VERA HVL, VIM, ModelSim, Xilinx FPGA Foundation series, Windows NT.

Contesse Semiconductor Corporation. October 2000 - February 2001. SONET Transport Overhead Processor FPGA (OHP155) Designed an FPGA as part of GigaStream Switch fabric chipset for collecting and thesis on oceanarium transmitting overhead bytes (both Transport overhead and Path overhead of SONET OC-3/3c frame) to/from optical interface. Abeng Essays? Developed architecture and coding of SONET Over Head Processing (OHP) FPGA interfaced with Spectra155 interface, High Capacity Multi-Vendor Integration Protocol interface (HMVIP) and CPU interface. Spectra interface consists of Transport OverHead (TOH) and Path OverHead (POH) interfaces to transmit and receive directions from Spectra chip. Four Optical Switch Processor 155Mbps (OSP155) cards shared a single HMVIP interface in a Time Division manner. Thesis On Oceanarium? The CPU interface is a Network Switching Processor (NSP) CPU interface to OHP FPGA for configuring. TOH/POH overhead byte information collected on HMVIP side is sent to corresponding Spectra155 devices.

Similarly overhead data that is sent by Spectra155 device is sent to HMVIP interface in correct time slot at correct frame location. There are eight dual port asynchronous RAMs implemented in this FPGA. Analyzed system requirement specifications and developed architecture for full functionality of abeng essays, chip. Coded transmit side modules of this architecture in Verilog HDL and tested functionality and thesis performance. Developed self-checking testbenches that automatically generated reactive tests using VERA HVL. Used Xilinx synthesis tool for synthesis of design and cover letter store generating sdf file. Did post-synthesis simulation of this design. Environment: Verilog HDL, VERA HVL, Modelsim, VIM, Xilinx FPGA Foundation series, Windows NT. Contesse semiconductor Corporation. April 2000 - September 2000. Designed an FPGA to thesis on oceanarium convert Fusion Omni-Connection for Universal Switching (FOCUS) bus interface to Packet on SONET physical interface (POS_PHY) bus interface, so that Vitesse s VSC9112 (OC-48) chip could be interfaced to abeng essays Vitesse s Network Processor IQ2000 through this FPGA chip.

Designed in Xilinx Virtex-E XCV-300E FPGA. Thesis? This FPGA had FOCUS 32 bus and POS-PHY-3 bus on either side to convert data (packets) from multiple analysis paper one bus protocol to other. Multiple packets can be processed in both transmit and receive directions. Used two FIFOs in Ping-Pong mode to carry Fcells in both receiver and transmit side. Did regression testing of Verilog RTL code. Generated random set of valid test cases using a seed value. Thesis On Oceanarium? Used Turbo C for writing a C code, which automatically selected a random number of test cases from the valid testcase library using a seed value.

Environment: Turbo C, Verilog HDL ModelSim, SignalScan, VIM, Windows NT. December 1999 - March 2000. Timing Controller Chip with mini-LVDS and FlatLink. Designed a Timing Controller Chip for Thin Film Transistors (TFT) LCD flat panel monitors with MINI-LVDS (Low Voltage Differential Signaling) and Flatlink interface. This chip id designed for customers like IBM, Samsung, LG with programmable display resolutions ranging from XGA to UXGA and to even support SXGA+ and W-UXGA.

Chip interfaces with CPU display card using TMDS (Transition Minimized Differential Signaling) Flatlink standard for digital transmission of Video output data at 1.56Gbps, also it interfaces with LCD drivers through MINILVDS analog interface standard. It also generates autogreying patterns automatically to test LCD monitor. Involved in digital architecture design of chip. Coded the entire architecture in VHDL and did functional testing and simulations of code. Used Shell Scripts for taking test bench (testing file used to test functionality of VHDL code).

Used Synopsis DC for synthesis. Performed post-synthesis simulations. Tested and verified actual performance of abeng essays, chip on LG s LCD monitor. Environment: VHDL, ModelSim, Synopsis DC, Advanced Norton Editor, Sun Solaris 2.1. May 1999 - November 1999. Design of Flying Adder Digital Logic for PLL (TFP8501) Chip. Designed a Scaler chip for LCD flat panel monitors to support resolutions upto SXGA+/UXGA and to maintain compatibility of various video cards and thesis LCD monitor resolutions by upscaling or downscaling resolutions whenever required. Involved in design of Digital logic for Flying Adder PLL (50MHz to letter 350MHz). Did coding of digital logic in VHDL. Thesis On Oceanarium? Performed synthesis of research, design using Synopsis DC. On Oceanarium? Used SPICE for abeng essays analysis the analog behaviour of timing critical nets.

Interfaced logic with analog PLL using SPICE. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, TI-SPICE, Sun Solaris 2.1. January 1999 - April 1999. Design of Analog PLL. Involved in the design of a TMDS receiver chip with HDCP for LCD flat panel monitor to support Transition Minimised Data Signaling protocol with High Data Content Protection. Rate of thesis, video data transfer on TMDS channel is 1.6Gbps. It enabled data interaction between CPU monitor video card and LCD monitors to be entirely digital. Designed architecture of Analog PLL (65MHz to 250MHz). Did Analog circuit design of effects of global term papers, Phase Frequency Detector (PFD), Charge Pump, Bias Generator and VCO.

Used Cadence Artist and Spice for analog design. Carried out all process corner simulations of individual design modules and completed closed loop simulations of PLL. Environment: Cadence Artist, SPICE, SimG, Sun Solaris 2.1. October 1998 - December 1998. Power Management Module for TFP401 Chip. Involved in the Design of a TMDS receiver core chip for LCD monitors.

It supports Transition minimized Data Signaling protocol from PC Video cards to LCD monitor. Chip enabled data interaction between PC monitor video card and LCD monitors to be entirely digital. Designed and coded the architecture for Power Management Module in thesis on oceanarium, VHDL. Did synthesis of this module. Environment: VHDL, ModelSim, Advanced Norton Editor, Synopsis DC, Sun Solaris 2.1. Mignion Systems Limited. July 1998 - September 1998. Design of Single Phase Energy Meter.

Designed and essay grow i i developed an Energy Meter architecture using ADSP2115 digital signal processor that calculates voltage, current, power, power factor, frequency and does harmonic analysis. Did assembly language programming of thesis, design. Successfully tested design on power lines. Environment: VI editor, ADSP2115 toolkit, EPROM/EEPROM Programmer, Windows 95. M. S. in regression paper, Microelectronics and thesis on oceanarium VLSI Design. ASIC/FPGA Design Verification Engineer. 2.6 years of fmcg resume, experience in FPGA Design ASIC Verification. Proficient with coding RTL Behavioral using Verilog and VHDL. Proficient with developing test environment for functional verification. Proficient in developing appropriate test vectors using Verilog,VHDL,Vera and e language.

Proficient in writing fully automated test benches. Experience with synthesis and optimization of Verilog/VHDL code Experience with FPGA implementation with Xilinx. Worked on Mentor Graphics Synthesis tool - Leonardo Spectrum, Synplicity Synthesis tool Synplify Worked on different simulator tools- Verilog-XL(Cadence), Modelsim(Modeltech) and VCS(Synopsys). Worked on thesis, Mentor Graphics Schematic Entry Tool – Design Architect. Worked on PCI 32 bit @33Mhz Worked with Specman, an cover store, ASIC Verification tool from Verisity Familiar with Vera, an ASIC Verification tool from Synopsys Familiar with DSL Protocol. Familiar with ATM Protocol.

Familiar with AMBA Bus Architecture. Familiar with 8085 and 8086 Architecture. Familiar with 8085 Assembly Language. Familiar with software languages C and Fortran. Good communication skills. ABC Chips Inc, San Jose, California. FPGA Design Verification Engineer. Name of Project: Network Processor Verification. Wrote test plan for one of the modules in the chip. Thesis? Developed the test bench for quality the module. Wrote test cases in Verilog.

Developed the different interfaces around the module. This network processor is designed to on oceanarium provide solution for 10 Gb Ethernet, OC-192 applications. The ingress device supports a POSPHY Level 4 (PL4 ) interface and the egress device supports CSIX interface to a switch fabric. Tools Used : VCS Modelsim. Language Used : Verilog. Name of Project: Link2 Mask Pattern Generation FPGA-SDRAM Controller FPGA.

Designed and Synthesized SWATH cycle Controller module. RTL coding done in Verilog with Verilog-XL and Synthesized using Synplify Developed the different interfaces around the Link 2 FPGA. Papers? Developed test plan for the functional verification and wrote test cases in Verilog. Done the thesis on oceanarium, module level verifications and top-level verification. Reported bugs and worked with the design team in regression, fixing the bugs. This module does interface controlling from the thesis, input side and takes the letter store, processed data to and from SDRAM controller. This module also does the thesis, interface to the output swath FPGA. This Link2 acts as a link between the input FPGA and fmcg resume SWATH FPGA.

This module does interface controlling from the on oceanarium, input side and effects term papers takes the processed data to and from SDRAM controller. Thesis? This module also does the interface to the output swath FPGA. This Link2 acts as a link between the abeng essays, input FPGA and SWATH FPGA. Tools Used : Verilog-XL (Simulator),Synplicity (Synthesis tool). Language Used : Verilog.

Silicon Grafic Systems, Bangalore, INDIA. IC Design Engineer. Name of Project: Rrishti-1-Trace Receiver ASIC Verification. Handled the responsibility of verification of all NRT transfers using IBM(Internal Bulk Memory) at module level and device level. Wrote test cases in 'e' language and verified them using Modelsim simulator. Reported several bugs in the design and on oceanarium worked with the designers to fix those bugs. The is a trace receiver, which provides the trace recording capabilities for one of the cover store, Emulation controller. The key features of the trace system ASIC are: Provides a maximum of on oceanarium, 4 channels operated at single edge clocking (positive edge, negative edge, positive edge and negative edge, or alternatively 2 channels operated with Bi-phase clocking scheme. An optional off-chip trace memory of essay grow i i up want, a minimum of on oceanarium, 128 M x 32 words provided by grow i i up want when, an EMIF(External Memory interface) using 64 bit SDRAMS serving all four channels.

On-chip trace static RAM memory organized as 32k x 64 (ie.256 bytes) serving all four channels. Thesis? This memory is used as channel temporary buffers and scratch memory when SDRAM is used to store channel data. Quality? trace packet width from 1 to 20 bits 167 MHz processing rate. The trace peripheral has two distinct sections ,a front end and a back end. Thesis On Oceanarium? The front end (TPFE)acquires the trace data presented by warming, the target and packs this data efficiently into thesis on oceanarium, 64-bit words. Cover Store? The Trace peripheral back end (TPBE) dispositions this data to trace memory, managing buffer locations, lengths, and host access to thesis these buffers independent of abeng essays, whether the storing process is active.

In short, the TPFE contains the acquisition, packing and buffering functions while the TPBE distributes the TPFE generated data into Trace buffers. Tools Used: Modelsim (Simulator),Specman Elite (ASIC Verification tool). Language used : VHDL (RTL), e language for thesis on oceanarium test cases. Engineering Design Center , Bangalore, INDIA. Hardware Design Engineer. Name of Project : PCI based high speed data acquisition card for signal Processing. Designed the Hardware . Designed the FPGA CPLD . Done the functional simulation synthesis.

Done extensive timing simulation with back annotating the sdf. Warming Term Papers? Done schematic Entry using Mentor Graphics Tool. PCI Add on card with PLX 9080 as PCI Bridge and on the local side uses one FPGA , which does all logic including bus arbitration and data transfer to FIFO . It actually acts as a local processor to PLX 9080. The input to the card includes 16-bit parallel data stream with strobe and 100 Mbps serial streams. Only one of these may be activated at a given time. The design goal is to accept data rate upto 40MB/s, but the testing will be limited to 20 MB/s transfer to memory. FPGA we were using was Spartan series XCS 40-4 ns.

VHDL entry, compilation and functional simulation is done through Model SIM a front-end tool, then after this we had done synthesis through Leonardo spectrum. Thesis? From that some edf(edif) files are generated and abeng essays we open those files in the Xilinx tool. We are using Xilinx tool as the back end. Here we place and route the on oceanarium, design and generate timing simulation data. From there one sdf(standard delay format) file is fmcg resume, generated. This includes all the thesis on oceanarium, internal delays of the device. The Xilinx tool also generates a test bench file. We will apply our stimulus to that Test bench and we make that as the essay grow up want, test bench for timing simulation.

So when timing simulation comes we load our design file and the sdf file and thesis on oceanarium simulate. Usually the FPGA has to be configured using a serial EPROM. But in thesis quality, our case since the FPGA is being configured from the thesis on oceanarium, system side, it cannot be a permanent data as from EPROM. So we are using the CPLD to configure the FPGA. It will take data through the local bus and load it to the FPGA.

Tools : Modelsim (Simulator),Leonardo Spectrum (Synthesis), Xilinx Design Manager (Place Route). B.Tech Final Year Project done at ER DCI , Tvm, Kerala, INDIA. Project Title: VHDL Model of UART. Developed the architecture Designed and done RTL coding in of global warming, VHDL. Done the functional simulation, synthesis and mapped to on oceanarium the target PLD. Tool Used : WARP 4.1. Simulator used : NOVA. Host Platform : PC under Win95. Device Mapped : CY7C341 from Cypress ( 192 Macrocell EPLD)

Study in detail one Standard HDL Study in detail about the PLDs Write own HDL code to build a model of one Standard UART chip with defined requirements Simulate the code for functional verification Synthesize and fmcg resume map the thesis, design to a suitable PLD. 10.1995 - 05.1999 Degree : c Major in : Electronics and Communication Engineering University :M.G University Kerala, INDIA . Got an award from Silicon Automation Systems ,BANGALORE for being the best project team for the quarter of the year 2000 for the Rrishti-1 Project. Got an award from the customer( Texas Instruments,Bangalore) for essay when outstanding Performance valuable contribution to the verification of Rrishti-1. Doing part-time courses in San Jose University for. Course 1- Advanced Logic Design (Winter 2001)

Course2-VLSI Design I (Winter 2001). Course3-Logic Design using HDL- Project- Bluetooth Transmitter. Course4-Logic Synthesis- Done using Synopsys DC. REFERENCES : Can be provided based on request. Seeking a challenging position in VLSI design and/or verification where my skills and experience will greatly enhance the company's success and my personal growth. H/W Description Languages: VHDL, Verilog. Place and Route: Lucent OFCC (ORCA Foundry Control Center), Altera Quartus, Xilinx Alliance. Synthesis: Exemplar logic (Leonardo Spectrum). Thesis On Oceanarium? Simulation: Modelsim, Quicksim from Mentor Graphics, VCS from Synopsys, VirSim (graphical user interface to VCS for debugging and viewing waveforms). Essay Grow I I When? Others: Mentor Graphics DA, Autologic II, Visual HDL, Renoir. Languages: C, C++, perl, Unix Internals like Shell and Awk.

Operating Systems: Solaris 5.6, FreeBSD 2.2.6, Windows NT/98. Networking Protocols: TCP/IP, UDP, ICMP, NIS, NFS, RIP, OSPF Others: PCI. Thesis? Revision Control: CVS. Saristos Logic Corporation, Mountain View, CA. Consultant, ASIC Engineer. As an ASIC Engineer, was a key individual contributor on a team responsible for conceiving, planning and implementing software and abeng essays hardware systems required to validate Storage Area Network (SAN) systems. Storage Area Network (SAN) offers simplified storage management, scalability, flexibility, availability, and improved data access, movement, and backup. Worked closely with the thesis, ASIC and hardware development teams with the goal of delivering quality ASIC silicon for advanced storage.

Register/memory access via PCI cycles or PCI DMA transfers or RTL hierarchy. Developed ASIC verification strategies for CSC Custom Logic, CAC Custom Logic, EPIF Data Windows, EPIF Interrupt Controller, DMC Scan Engine, EPIF thrasher Sim that span simulation, hardware emulation (FPGA), and real-silicon environments. Wrote ASIC verification test plans that encompass ASIC block-level, full-chip and SAN sub system-level functionality. Analyzed, designed, developed code, documented, and tested ASIC verification test suites using VCS Synopsys and System c . Cover Letter Store? Migrated test suites developed in the Verilog simulation environment to both hardware emulation and final silicon lab verification environment. Each Verification Sim was tested with a model which also takes the thesis on oceanarium, same input vectors and generates expected value for letter that input vectors. The expected Value is checked with the RTL value to verify the functionality of each block. Wrote high level monitors and thesis stimulus models to automate the verification process. Analyzed the abeng essays, timing for Data Windows using Logic Analyzer thus reducing the time for Data Window writes from 1.5 hrs to 18 mins for on oceanarium 1GB of memory on Hardware Emulation Platform. Wrote Scripts for HEP (Hardware Emulation Platform) regression suites. Participated in effects of global papers, estimating verification development schedules and on oceanarium ensured on time delivery. Infotech Systems Inc., Boston, MA.

As a Design Engineer was responsible for conceiving, designing, developing and testing digital circuits for both ASIC and FPGA. Designed and tested the digital portion of the chip for abeng essays television. Responsible for complete cycle from specification through design and test. Designed the digital circuit using VHDL. Synthesized using Leonardo Spectrum, targeting it to Lucent's ORCA series FPGA.

Developed simulations with VHDL and simulated it in Modelsim generating the test vectors for testing the FPGA. Developed Verilog testbenches and thesis on oceanarium tested the circuit back annotating with SDF. Checked the timing of the design generating test vectors for letter store testing the ASIC. Designed and tested Inter-Inter Connect (I2C) circuitry in on oceanarium, VHDL and abeng essays Verilog using Visual HDL. Thesis? I2C bus defines a serial protocol for passing information between agents on the I2C bus using only multiple analysis, a two pin interface. Thesis? Designed a I2C bus slave interface controller using Visual HDL. Essay Grow I I Up Want? Synthesized the circuit using Leonardo Spectrum and targeted to Lucent's ORCA series FPGA. Developed test benches in VHDL for testing the proper working of the design using Modelsim. On Oceanarium? Designed and tested the read channel chip. Worked on three different versions of the read channel. Designed the FPGA using Visual HDL generating the RTL for the design.

Tested the design writing VHDL test benches for regression analysis research paper the proper operation Placed and routed the design using ORCA Foundry Control Center targeting to the Lucent's ORCA series FPGA. Evaluated place and route tools for the read channel chip. Evaluated the thesis on oceanarium, design to test the read channel chip with various FPGA place and route tools. Tools evaluated include Xilinx's Alliance, Altera's Quartus tool and letter store Lucent's ORCA Foundry Control Center. Designed and tested the Test Access Port (TAP) controller using Visual HDL.

Designed an thesis, IEEE standard TAP controller. Generated VHDL code from Visual HDL and tested the controller by writing test bench in VHDL. Simulated it using Modelsim. Developed Perl script for conversion of fmcg resume, Spice netlist in to VERILOG netlist. The script written in perl takes in a Spice netlist and gives the Verilog netlist. Developed testbenches for the Verilog netlist for on oceanarium the million-gate chip. Developed test sequence for this verilog file for thesis quality checking the thesis, operation of the chip.

Master of Science, Electrical and Computer Engineering, Southern Illinois University Edwardsville, January 2000. Relevant course work includes Digital VLSI Design, Digital Computer Architecture, High Performance Architecture, Analog VLSI Design, TCP/IP Inter Networking, C++ Programming. Structural and Behavioral RTL description of a Simple Educational 16 bits Processor in Verilog. The structural description of the data unit, the control unit, SRAM and other modules were coded and tested. Warming Term? Other Projects Design of a Linear Interpolation Filter using Verilog and on oceanarium full custom IC layout. Fmcg Resume? Design of a Simple Educational Processor using VHDL. Designed and simulated a sigmadelta modulator for an EEG IC. Bachelor of Engineering, Electrical and Electronics Engineering, University of Madras, May 1998. Reference: Furnished upon request. ASIC-FPGA Design Verification Engineer.

To work where I am given the opportunity to assionately exploit my knowledge to the fullest level of thesis, satisfaction both personally as well as for the company I serve on the whole. SUMMARY OF EXPERIENCE: Over 7+ years of experience 5+ years of experience in Hardware Design, Development Verification using ASIC, PLD, CPLD FPGA Designing Verification, Board simulation, ANSI C, Assembly, C++, PLI, PCI, VLSI, PCB, Verilog, Synopsis, VHDL,VERA, Gigabit Ethernet,(Networking) SONET,ATM, Device Drivers , Win Board, Synthesis, Verification of Design.CMOS,Embedded System (SOC),Real Time Operating System RTOS), VxWorks, Logic Analyzer, Simulator, Emulator Programming of RAM(SRAM DRAM) With excellent analytical and programming skills. Very conversant in documentation, presenting prototypes, client interaction, quality assurance. Effects Of Global Papers? Good communication and interpersonal skills. Strong Points include quicker grasp to new concepts, the ability to pursue matters in great detail and thesis on oceanarium able to work in a team. Bachelor of thesis paper, Electrical Engineering from Bangalore University. Jan 2000 - Present DSSABC Software, Inc., CA, USA.

Feb 1998 - Nov 1999 FDD Containers Limited, London, UK. Oct 1996 - Jan 1998 RANDY ENGINEERING, Tripoli, Libya. Jul 1994 - Sep 1996 Advanced Systems Solutions, Delhi, India. Client: Smart Networks Utilties, Santa Clara, CA Aug 2000 to Present. Scope of the project was to design develop a micro controller chip for networking purpose on networking boards, which sends and receives data digitally Supports Gigabit Ethernet on Fiber Optics. My Role: As a team member I was involved in.

FPGA ASIC design Wrote verilog HDL code for thesis on oceanarium design. Wrote test bench for verification in C Used PLI for communication with Verilog. Integration testing verification. Functional testing verification. Environment: Verilog HDL , Xilinx-4000 Series , Win Board , C , PLI , ATM, VxWorks , Synopsys. Client: Digital Design, Santa Clara, CA Jan 2000 to letter store Aug 2000.

The objective of this project was to design, developed the data networking boards and test benches for thesis verification purpose of pre written functions in verilog . Simulation and hardware development of thesis quality, communication subsystems using the sections reconfigurable-prototyping. Design, simulate, and test digital hardware. Thesis? Developed data networking boards, and backplanes. Performed the effects of global warming term papers, design, capture the schematics and oversee the board layout. Performed board simulation and signal integrity. Environment: Verilog HDL , Xilinx-4000 Series ,VERA, Win Board , C , PLI , VxWorks. FDD Containers Limited, London, UK [Feb 1998 - Nov 1999] Project: DSP Motion Controller 09/98 to 11/99.

Client: FDD Container (UK) The purpose of the project was to design and develop micro controller chip 80188EB for controlling the motion of Mechanical Equipment Boomer there was servo motors which controls Boomer Motion.Servo Motor was controlled by the tech called DSP motioncontroll (Digital Signal Processing). The RTOS was designed implemented on higher priority algorithm, the thesis, signals of higher priority is served earlier than a signal with lower priority. The code was written in c inline Assembly on Host Computer. Design, simulate, and test. Essay Grow Up Want When? Programming of SRAM DRAM. Thesis? Writing Test Benches for Verification in verilog C. Abeng Essays? Performed board simulation. Environment: C, ASIC, Test Bench for thesis Verification, Perl, Synthesis, Verilog, Inline Assembly, Target 80188EB,RTOS VxWorks. Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer.

Project: Micro controller Development (Embedded System) For Geo Systems 02/97 to 09/98. The purpose of the project was to design and develop micro controller chip 8051EB for controlling heat Generation in Turbines of thermo electric Power plant. The processor controls the steam temperature. Which receives the signals from Boiler sensors. Regression? If due to thesis on oceanarium any reason the temperature goes below specified level the alarm will be activated. It had the provision of printing the Time versus heat graph controlled by the processor 24/7.Programming of the RAM was done by thesis quality, c inline assembly. Device programmer was used to on oceanarium copy the image files on fmcg resume, the chip. Design, simulate, and thesis test micro controller chip. Programmed SRAM DRAM. Wrote verification code in verilog C Performed the thesis quality, design, capture the schematics and on oceanarium oversee the board layout. Performed board simulation.

Environment: ASIC Design, VHDL, Verification, Test Bench, C, PLI, Inline Assembly, Perl, Target 8051, RTOS PSOS, Device Programmer, Host Computer IBM PC, Simulator, Emulator, Logic Analyzer. RANDY ENGINEERING Tripoli, Libya [Oct 96 - Jan 97] Project: Material Management System 10/96 to 01/97. DOS based Stand alone Database Application developed under C++ for Civil Engineers providing Menu Driven User Interface for i i up want calculating the thesis on oceanarium, Quantities of material required and abeng essays its Costing, providing an easy access to feed the thesis on oceanarium, User input data. Its related Quantity and Cost will be calculated automatically with the abeng essays, help of in-build functions related data Information that is also capable of modifying as per the user specifications and standards.

It takes the Complete Details of a building (to be constructed) by on oceanarium, providing an abeng essays, Interface and Calculates the quantity of material required with its estimated cost, as per thesis, the standards specified. It provides an easy access for modifications. Environment: C, UNIX and of global warming MS DOS. Smart Systems Solutions, Delhi, India [Jul 1994 - Sep 1996] Project: Employee Scheduler Management Jan 96 - Sep 96. A standalone Application developed using Visual C++ 5.0, for on oceanarium Microsoft Windows95 and Microsoft Windows NT, to be used as the Employees Schedule and regression research its Related Information, in a Large Companies, Hospitals etc.

Developed system allows you to thesis on oceanarium get detailed Information with Graphical Representation related to effects of global term an employee and its Schedule (Working and Leave Duration's Designed for a Complete year) Allows Online Modifications for Updating the Individual Schedule of an employee, and its related information. Which intern Automatically updates the related Schedules of other employees if desired. Environment: Visual C++, MS Windows 95. Project: Management and Security of File System Feb 95 - Jan 96. An Application Program of which the Core Part is handled using C++, and thesis on oceanarium the GUI (Graphical User Interface) is handled using Visual C++ for Microsoft Windows 95 and fmcg resume Microsoft Windows NT.

Which allows the thesis, user to maintain its File System with Security, providing File and of global warming papers Application Locking. With which it is possible to lock any Executable Program from being unauthorized Access, by providing Password facility. It is Capable of Locking Windows95 from being Loaded Unauthorized at the Boot time. Provides an Easy and Quick File Search. Provides Quick Access to file Opening and Executing. Provides File Viewing facility before editing the files, giving an Easy access to Editing. Environment: Turbo C++ 3.0, Visual C++ 5.0, and thesis on oceanarium MS Windows 95. Project: Standard Product Impress Jul 94 - Feb 95. Impress is a standard integrated package targeted at the Printing and Advertising Companies as the major customers. It was designed and developed by Thomson Technologies, India. The product included modules such as Financial Accounting, Purchase, Sales, Inventory and Production (Studio Section Camera Section).

Was a member of the team, which designed the analysis paper, system? Other responsibilities included coding and testing. Thesis On Oceanarium? Developed 12 forms and various other Reports. Environment: Visual C++, Visual Basic, MS Windows 3.1. Visa Status : H1B. References: Available on request. Nine and abeng essays a half years of on oceanarium, strong experience in Verification of ASICs using Verilog, VHDL, VERA, Verilog -XL, Synopsis VCS, Mentor Graphics Co-Verification Environment, Assembly Language on Unix platform.

Expertise in multiple paper, writing Verilog Model, developing test plans, Quick test writing and setting up Verification environment in thesis on oceanarium, Verilog/VHDL. Good knowledge of PCI protocol. Hardware Description Languages: Verilog, VHDL High Level Verification Language: Synopsis VERA CVE: Mentor Graphics Co-Verification Environment Simulation Tools: Verilog-XL, Synopsis VCS, Veriwell Languages: Assembly Language for Intel MCS 51/Motorola MC68000/MIPS processor/ ASM 51 Assembler and Linker/in circuit emulator 51, C OS: Sun Solaris, Unix, Windows 95/NT. LSX Technology, Inc., Moutain View, CA. August 01 till date.

Verification of PCI bridge( PCI to local) PCI 9656. Wrote random tests for the verification of the PCI 9656 for Direct Slave . Direct Slave means that the chip is the slave on the PCI bus, Direct master means that the chip is the master on the PCI bus. Worked on PCI compliance testing for quality the PCI 9656 using Synopsys PCI compliance suite. Worked on FIFO testing. On Oceanarium? There were 2 FIFOs. One for the Direct slave read and the other for the direct slave write. Wrote various test and verified the of global term, functionality of the FIFOs for both the empty and full condition. Thesis? There were numerous condition to quality paper fill and empty the on oceanarium, FIFO. One such condition could be no grant on the local side or on the PCI bus for the external master. Thesis Paper? The chip has 3 modes namely M, C and J modes . These modes are the thesis on oceanarium, local bus types. Fmcg Resume? M mode is thesis on oceanarium, 32 bit address/32 bit data, non multiplexed direct connect interface to MPC850 or MPC860.

C mode is 32bit address /32 bit data non multiplexed for cover store intel processor i960 and J mode is 32 bit address/32 bit data multiplexed. Environment: Verilog, Sun Solaris. Visitor Graphics Corporation, CA. January 01 - till date. Field Application Engineer. Was responsible to give product presentation, demonstration for thesis on oceanarium the Seamless CVE (Co- Verification Environment). The Hardware and Software Co- Verification helped in software debugging, shirk the quality, system integration time and avoid prototype respin. Was required to perform evaluation of the product at the customer site.

Satisfied the customer about the on oceanarium, utility of the product through a question/answer session and with follow up visits to potential customers. Performed evaluation of the product and against the product of competitors. Environment: Verilog, CVE, Assembly, Sun Solaris 2.x. Advanced Networks, CA. December 99 - December 00. Verification of abeng essays, a Packet Classification ASIC. The ASIC was used to offload the network processor of the job of classification of the packet. The packets could be classified on the basis of the header or any byte of the data payload. The ASIC had system bus interface, ERAM interface, AOC PIB modules. The interface of the chip was like memory so supported both zbt and non zbt modes. The system bus could be configured as 64 bit or 32 bits.

The speed of the thesis, ASIC was in the range of 50 - 100 MHz. Wrote diagnostics to verify the system bus interface using Verilog. Build the Chip Verification Environment using VERA. Debugged the failing test cases. Abeng Essays? Found several bugs and fixed the bugs.

Environment: Verilog, VERA, VCS, Sun Solaris 2.x. June 99 - November 99. Verification of a Networking SOC. Involved in Verification of a Networking SOC having MIPS Processor, SDRAM Memory, MAC, PCI and HDLC. Was responsible for Verification of the bridge between the MIPS Processor and thesis the Toshiba Proprietary bus using Assembly and effects of global Verilog in a multi master System Verification environment. Developed several MIPS Assembly and Verilog based test to verify the functionality of the G bridge and HDLC.

Translated the unit level test cases for HDLC to on oceanarium system level tests. Fmcg Resume? Verified the thesis on oceanarium, tests at full chip level. Found bugs, notified the designer and suggested fixes. Environment: Verilog, Assembly, VCS, Unix. January 99 - May 99. Verification of a Network Output Controller. Network Output Controller was responsible for moving data (packet) from the of global warming papers, packet buffer (external SRAM memory) through the port FIFO s to the network interface. Verified the above functionality of the on oceanarium, NOC by writing the functional models in Verilog. Verified functional models.

Verified Packet buffer read and of global warming papers writing. Packet buffer was read and written as 1024 bits at a time in 11 clock cycles. Verified the packet Queue (PQ) which performed queuing and dequeuing of the packet through the star address in thesis, PB and abeng essays the skip over mask. Verified Packet Receiver which received packets from all the 50 ports at the network interface in the TDM manner. Functional model of the thesis on oceanarium, NOC was written before the RTL could be plugged with other functional models.

RTL replaced the NOC model. Developed the cover letter, test bench and wrote task for thesis on oceanarium specific functionality. Developed test plans, test cases for the Chip Level Verification of the ASIC using Verilog. Found and fixed bugs. Environment: Verilog, Verilog -XL, Sun Solaris 2.x. March 98 - December 98. Design and paper Verification of thesis, HDLC Controller (Project Lead)

Involved in Design and Verification of HDLC Controller with a generic 8- bit microprocessor interface. Cover Store? The HDLC controller framed according to the HDLC protocol. The frame checksum generator and checker were implemented. The controller was to the ITU Q 921 specification. Thesis? Designed the HDLC controller. Involved in portioning of the design into Transmitter and Receiver. Abeng Essays? Verified the HDLC. Synthesized the HDLC. Environment: Verilog, Verilog-XL, Sun Solaris 2.x. Sonet Technologies Pvt Limited. January 97 - February 98.

Development of thesis, VITAL ASIC Libraries. Verilog to VITAL converter was used to translate the fmcg resume, Verilog Structural Model to VITAL. Thesis? Testing was done on Quick HDL simulator, which was one of the sign off simulator for LSI logic. Was responsible for Conversion and Simulation. Environment: VHDL, Quick HDL, Unix.

Sonet Technologies Pvt Ltd. April 95 - December 96. Development of Test Bench for thesis paper BUS Interface Model for MC68030 and MC68020. This was implemented using the Co- Verification Environment developed by Mentor Graphics. Thesis On Oceanarium? The hardware (Verilog/VHDL) was simulated on HDL simulator like QuickHDL and the software was simulated on the software simulator (different for each processor). The Bus Interface Model was specific to cover store the processor and on oceanarium generated bus related cycles for the processor depending on the type of access. The tool was used in designing embedded system where the software could be verified against the hardware before the essay grow i i up want when, hardware prototype was made. Environment: Verilog, VHDL, CVE for Mentor Graphics, Unix. Parametric Network Limited.

November 91 - March 95. Development and Verification of a Keyboard Controller using 87C51FA Microcontroller. Developed assembly language programs. The keyboard and the system (486 PC) serial communication was established and keys were scanned. Whenever any key was pressed, the make and the break key codes were sent serially in thesis, an 11-bit format to the system (486 PC). Provision was made for interfacing more than 1 keyboard with this keyboard controller. This also included the standard PC keyboard. Environment: Assembly, Unix. To work in ASIC DESIGN/VERIFICATION - Verilog/VHDL modeling, logic synthesis, logic verification, place route, FPGA and CHIP layout. VLSI Logic design - Complete design flow from multiple regression analysis research paper RTL to layout. Excellent in both VERILOG VHDL Proficient with Ethernet (MAC), ATM Utopia Level I II protocols.

Complete understanding in architectures of PCI OHCI. Proficient with USB. Thesis? Knowledge in essay when, Unix, Perl and 'C'. Knowledge in VERILOG PLI CONCEPTS. Good experience in Digital synthesis and Place Route. On Oceanarium? Configuring CPLD with bit blaster using MAX+plus II. Expertise in Altera /APEX FPGA. Experience in Assembly Language. Analyzed circuits using SPICE. Simulation : Verilog XL from Cadence 2.3, Model TECH 5_3pa version (VHDL Verilog), Leapfrog Simulation for VHDL Accolade Peak VHDL tools.

Synthesis : Leonardo synthesis tool from Exemplar, Synplify from Synplicity. P R : Altera MAX+plusII , Lucent , Quarters Tool for when APEX Devices. Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Others : Signal Scan and thesis De-bussy for waveform generations Assembly Language : Programming Logic works, C, PERL,UNIX SPICE, MAGIC IRSIM. 'C' Compiler : Green Hills Software. Company I : Analog Systems, CA. Duration : Jan '00 - Till Date. Designation : Member Of Technical Staff. Company II : Trenton Chip Devices, Inc., CA. Duration : May '99 - Dec '99. Designation : VLSI Design Engineer. Company III : Trenton Chip Devices, India.

Duration : May '97 - Apr '99. Designation : VLSI Design Engineer. Company : Analog Systems , Inc. Location : Santa Monica, CA. Designation : Member Of Technical Staff. Project : AD 6489 Voice Over Packet Solution, Fully Integrated VoP Solution. Duration : August 2000 - Till Date.

The Si was taped out on Oct '2001. Of Global Term Papers? The Total No. of gates is on oceanarium, 1.2 Millions. It operates on 125 MHz. It's a .18 micron technology. The AD6489 family of packet processors performs voice and data packet processing for the SOHO (Small Office/Home Office). SME (Small Medium Enterprises and RG (Residential Gateway ) Market. The features it supports is thesis, Layer 3 + Software, Voice and thesis Fax, Signaling, Networking Management, Security, Physical Interface, ATM Support, AAL5, IMA, FR and PPP and Memory support. The AD6489 solution helps the system vendor go to market faster by providing a highly -integrated SoC. The SoC comes with a reference board and complete software solution for both VoIP VoATM based solution. A Powerful Application (API) and fmcg resume plenty of processing power are available for thesis on oceanarium the system vendor to provide differentiated value addition to the system.

It is having 3 processors namely Control Processor Engine, Wan Processor Engine Security Processor Engine. The AHB bus being the major interface between these processor and the Peripherals, which includes like (UTOPIA, HDLC, UART, GPIO, USB, SPI). There is an intelligent DMA, which does the memory transactions between memory and the processors. Then for the WAN interface we have 10/100 EMAC and also supports external PCI USB. It has on chip SDRAM controller flash controller 200KB of on-chip memory for voice and abeng essays data processing. Developed Designed in verilog the intelligent DMA block. Which does all the major operation for the above chip AD 6489 the rams. Created Testbenchs for the blocks like UART, SPI DMA.

Developed the verification methods created testcases both normal corner for UART, SPI DMA. On Oceanarium? Did the RTL netlist simulation for UART, SPI, DMA. Did the other testing like JTAG, MBIST, EMAC, PCI, USB Testing on abeng essays, the RTL netlist level simulations. Did the random testing for the above blocks at the system levels and also for the other blocks. Verilog XL from thesis Cadence 2.37 Signal Scan/De-bussy for waveforms. Duration : Feb' 00 - July '00. Designed, developed verified the UMAC in VERILOG. This s going to letter store be used and cable modem chip. The design was target for APEX FPGA from altera 20K200. The design basically consists of thesis on oceanarium, 5 interfaces. Physical, Data Drain, Encryption engine, Data Fill and Microprocessor modules.

The PHY interface can get the data from simultaneously from 8 devices and paper gives to Data Fill interface via data FIFO. It also stores the relative information in another FIFO called pointer. From these FIFO Data fill interface dumps the on oceanarium, data to the memory . The data drain gets from memory and gives to the microprocessor module. The design operates in 3 different frequencies. The input data is coming at cover letter store 10Mhz, which is to the phy interface. The microprocessor interface is working on 60 Mhz and the rest of the interface is working on 40Mhz.

Verilog XL from Cadence 2.37 Signal Scan/De-bussy for waveforms. Max-Plus II for P R. Synthesis by thesis, Syniplify from synplicity. Duration : Jan '00. Implemented the SPI interface in VHDL between SPI and external BUS interface used for IMA. Leapfrog Simulation for VHDL. Company : Trenton Chip Devices , Inc.

Location : Sacramento, CA. Designation : VLSI Design Engineer. Project : Transceiver Subsystem. Duration : Nov'99 - Dec '99. Designed Developed controller for DPRAM (in verilog) which is used get the Data from ATM fpga and feed to the microprocessor. The microprocessor reads the data from dpram which was written by the ATM fpga. Designed the thesis, code in Verilog. Compiled and simulated in MTI Verilog simulator (Model Tech).

Renoir Tool and Xilinx Foundation series 2.1I from Mentor Graphics. Project : Internet Data Storage. Duration : Aug'99 - Oct'99. To store the Data into the Disk Array through the user in the internet.The block gets the thesis on oceanarium, data to be written into the disk module from the memory for which the CPU provides the address. The data with the parity is then stored in the memory. Fmcg Resume? While reading the data, it regenerates the parity and checks with the parity that is on oceanarium, read. On error, the letter, date is invalidated. The parity and data are stored in the memory through the interface. DMA is used for on oceanarium reading and writing the effects of global term, data into the memory for burst of transaction. On Oceanarium? Developed Designed the logic in verilog which is specific to Disk Module and it provides the abeng essays, following functions:

Raid Parity generation Raid Parity verification Raid Parity reconstruction Interface to the Main Memory DMA. Compiled and on oceanarium simulated in MTI Verilog simulator (Model Tech). Duration : May'99 - July'99. The OC3 FPGA communicates using either ATM Cells or POS. In ATM mode, the data path is between the SAR and the PHY via the UTOPIA slave level 1 to UTOPIA master level 2 interfaces. Utopia1 slave is running on 25 Mhz and data rate is 53 bytes.

UTOPIA 2 master is running on 33 Mhz and date rate is 64 bytes. There are two downstream FIFOs and two upstream FIFOs. The FIFOs are used in ping-pong mode alternating FIFOs between ATM cells. No parity or packet error reporting of any kind is supported. Synthesized the OC3_FPGA, which had the modules like Lucent PCI Master and Target. Module ware Utopia Master and Slave. Interface Data Path Between Tetra and multiple regression analysis research SAR.

Completed Place and Route of the thesis, above project which was mapped with the Orca Foundary Family, of the Architecture 3T800 Series. Totaled to 390 numbers of PFU. Synplify Syntheses Tool From Synplicity V 5.1.4. Lucent Place And Route Tool Version 9.35. Company : Trenton Chip Devices. Location : Chennai, India. Designation : VLSI Design Engineer. Project : Verification Of USB Open Host Controller. Duration : Jan' 99 - Apr'99.

Member in the verification of grow i i up want, Open Host Controller, which controls the transaction running on thesis on oceanarium, USB bus. It fetches the i i, Endpoint Descriptor and Transfer Descriptor from thesis memory and effects of global warming term performs the thesis on oceanarium, appropriate action depends on the information from the Descriptor. Effects Of Global Papers? These Descriptor includes the information about the device. Developed the PCI Test Bench for OHCI. Created testcases for the functional verification of OHCI. Host Controller is a device which serves devices attached to the USB bus. It is interfaced to the PCI bus for accessing the thesis on oceanarium, system memory. Designed this core using both VHDL and VERILOG.

This design has different types of fmcg resume, modules. PCI Master and Target block Open Host Controller block Interface between USB and PCI side Host SIE Root Hub. Project : Design of PCI master/target. Duration : July' 98 - Dec' 98. Designed OHCI compliant PCI master/target function. Done testing on this module. Carried out synthesis of all these modules using EXEMPLAR LEONARDO. Done Place and Route using ALTERA MAX+plusII. PCI Master initiates transaction on the PCI bus for getting the thesis, ED/TD's or data's for USB devices from abeng essays main memory or updating the data from USB devices to main memory. PCI target responds to configuration transaction's and thesis on oceanarium other Bus Master's initiates transaction. Implemented the logic for PCI Target and PCI Master.

Tested the whole project using ModelTech simulator. Synthesized the grow, logic using Exemplar's Leonardo tool. Max+plus II tool is used for thesis Place and Route. Thesis Quality? Mapped the PCI core into thesis on oceanarium, the Altera Flex10k30 device. Mapped the USB side core into the Altera Flex10k100A device. Mapping the whole design into ASIC Library and testing is in progress. Total gate count for OHCI project is paper, 33,000 gates. Project : Design and verification of Hearsee-USB Logic.

Duration : Jan'98 Jun'98. Hearsee is a video compression chip used to capture active video pixels from the digital camera, scales down to 2:1/4:1 ratio, compress the thesis on oceanarium, pixels and deliver the encoded data to the computer through USB. It consists of abeng essays, video camera interface, scalar, a high quality compressor and USB interface. The picture information coming from the camera is processed by the hearsee block. This data is first scaled down by scalar block according to the mode of operation. Thesis On Oceanarium? This scaled down data is compressed by the compressor block. This compressed form of data is research, sent through the USB cable. Designed the on oceanarium, data flow for abeng essays the still video capture mode of Hearse Created testcases for the functional verification of Hearsee individually in still, motion capture modes as well as combination of still-live modes Performed simulation in modeltech VHDL simulator. Project : Verification of USB Device Core. Duration : Nov' 97 - Dec' 97. Involved in the verification of a USB Device Core.

Project : Design of FIFO. Duration : Oct' 97. Designed a 8-bit 256 deep FIFO with revert and latch read pointers. Used Model Tech VHDL/Verilog Simulators and on oceanarium Leonardo Synthesis Tool. Target technology was Altera FLEX10K device. Project : Design of a bit stuffer. Designed the bit stuffer in logic works, using VHDL and Verilog. Project : Design of a Traffic Light Controller and fmcg resume Stepper Motor. Duration : Aug' 97. Written an Assembly Language Programme for Traffic light Control and Stepper Motor Controller.

Used the thesis on oceanarium, add-on card with 8253 Timer and PPI chips along with 8379 for testing of this design. Bachelor of Engineering (Electronics and Communication) 1997. Madras University, INDIA. 7.5 GPA. REFERENCE : Available Upon Request. 1200 Moonlight Dr. Santa Clara, CA 95127. Valid H1-B till 2004. Domain Skills: Micro controller and essay grow up want Microprocessor design and verification.

Understanding of communication Protocols. Applications: Digital Design Methodology Network Flow, RTL coding, Synthesis, Simulation of full chip and block level designs. Functional verification of thesis, full chip design, Physical design skills at chip level, Physical Verification, Writing Software utilities Languages: PERL and Shell Script, C, HTML CAE Tools: Verilog-XL, NCVERILOG, Polaris, Synopsys Synthesis tools, Cadence Composer, Compass tools, DRACULA for physical verification, TransEDA and HDLScore for code coverage, AVANTI tools. OS: UNIX, SUN-OS, and effects warming papers WINDOWS. Network Alliance Corporation. Verification Of a Re-configurable Network Processor (09/01 - present)

Client: Crystal Systems, Santa Clara, CA. Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at the networking applications. Responsibilities require me to thesis write directed tests to verify the tile block and random tests to verify concurrency. Code Coverage Analysis (07/01 - 08/01) Client: Vertex Networks, Santa Clara, CA. My role required me to store analyze the thesis on oceanarium, test vectors from the fmcg resume, viewpoint of code coverage, and furnish suggestions to the verification team as per the findings. Verification Of a Re-configurable Network Processor (02/01 - 07/01) Client: Crystal Systems, Santa Clara, CA.

Crystal's CS2200 is a re-configurable processor with embedded ARC core mainly targeted at thesis on oceanarium the networking applications. Cover? Responsibilities required me to thesis write tests to verify the fmcg resume, various modules of the thesis, chip, e.g. fabric, road-runner bus, code generator. I also did the code coverage analysis to optimize the test suit for letter better fault grading. Teriola India Ltd., Gurgaon, India. VLSI Design Engineer. Design Of a CAN protocol implementation (11/00 - 01/01) The Control Area Network (CAN) protocol is used in automobiles for communicating between various controllers inside the vehicle. Thesis? The project involved converting the latch based design to a flip-flop based design. Of Global? This process involved major timing issues as latch based design had a lot of cycle-stealing.

Responsibilities required me to convert the thesis on oceanarium, RTL to analysis paper flip-flop based design and simulate the design to see there are no issues with the conversion. Finished my part in record time. Design Of a microcontroller (10/99 - 10/00) The micro-controller is to be used in automotive Industry for thesis on oceanarium anti-skid braking. It is based on Motorola's Mcore processors. Responsibilities required me to verify, Synthesize and PR the Timer block. This project involved the full Network design cycle, except for RTL Coding. MARCUS Tech, Bangalore, India. VLSI Design Engineer. Design Of a 16 Bit RISC Processor (08/99 - 09/99) It is a general-purpose 16-bit microprocessor core, designed to be used in effects warming, DSP engines.

The project involved full chip design using Design Reuse methodology.Responsibilities required me to on oceanarium design, verify and synthesize the Program Counter block. Functional Verification of store, a 16 Bit RISC Processor (02/99 - 07/99) ARC85 is a family of on oceanarium, general-purpose 16-bit microprocessor cores, primarily designed for embedded applications. The project involves the Full Chip functional Verification of the microprocessor core. The chip was verified using Compass-generated vectors. I was responsible for writing the test-bench for multiple regression research paper the full chip simulation.

Later, the Compass-generated vectors were used to thesis generate the Verilog format vectors for full chip testing. The work also involved the testing of quality, vectors on the netlist generated by the Synthesis tool. Netlist to RTL conversion was also part of the project. Redesign of 8-bit Microcontrollers(SPC700 series) for Sony Corp(04/98 - 02/99) SPC700 series is a general-purpose programmable 8-bit microcontrollers originally designed by SONY. The project involved the redesign of the whole series from 1.4 Micron technology to 0.7 micron tech. It also involved dynamic to static logic conversion. Participated as a member of a 3 member team.

Redesigned 2 of a series of 4 microcontrollers. The redesigning involved Logic Conversion, Schematic Entry, PNR and Functional Verification at the block level as well as the full chip level. On Oceanarium? Played major role in setting up the test environment for the full chip. Executed the project successfully in the first go. Developed a software utility, indigenously, using Perl Shell scripts to convert the stimulus file from ANDO-DIC 8031/32 format to a Verilog compatible format. This saved a lot of expense to the company. Granada Consultancy Services. Assistant System Analyst. American Express Milleniax Conversion (10/97 - 03/98) The project involved the of global term, modification of the existing code for American Express to make it Y2K compliant. The project was divided in various implementation Groups (IG's).

Each IG was responsible for modifying and testing a market. Participated as a member of a 4 member team and on oceanarium later as an Implementation Group leader. Training in Software Development Process (07/97 - 09/97) It involved training on different Software Platforms, Programming Languages and abeng essays Graphical User Interface. It also consisted training on Software Development Methodologies. It also involved a project in C on UNIX to on oceanarium manage an employee database. Advanced Chip Synthesis Workshop (2000) The workshop was conducted by Synopsys Inc. at Teriola, Gurgaon. Fmcg Resume? It focused on advanced chip synthesis methods.

1997 B.Tech. in thesis, Electronics Communication Engg (DGPA 8.28) IT, BHU, Banaras, INDIA. Project : Implementation Of Star LAN using PC-AT (11/96 - 04/97) The project involved implementation of fmcg resume, Star-LAN using PC_AT's to connect two labs in thesis on oceanarium, Electronics Department of IT,BHU. The process involved PCB design and C coding of of global, device driver for the LAN card. Sr.chip designer, with MSEE in VLSI, from Nortel Networks, experienced in ASIC, FPGA, HDL, C/C++, ATM, IP 10GE, SONET and thesis RT embedded, applies for ASIC / FPGA design or H/W position. MSEE in letter, VLSI Design, ECE of UNB, New Brunswick, Canada. Ph.D.

Candidate in Computer-Aided Design Center, China. MSCE in Computer Engineering, WU, China. On Oceanarium? BSEE in thesis, Electrical Engineering, WU, China. SUMMARY OF QUALIFICATIONS. Skilled in on oceanarium, all phases of Front-end ASIC, FPGA design, including architecture development, writing specification, partitioning, RTL coding, function simulation, synthesis, timing analysis. Skilled in Verilog, VHDL and SystemC, Specman, Vera, C/C++ and thesis quality tools: Synopsys's DC, Primetime, GNU, VCS, Verilog-XL, NCverilog, Modelsim, SignalScan and Synplify, Xilinx. Thesis On Oceanarium? Skilled in board level hardware design, Schematic, Simulation, and PCB in OrCAD, Viewlogic. Rich experience in H/W and quality S/W co-design for thesis MPU-based embedded application systems. In-depth working knowledge of ATM, IP, MPLS, GE, SONET and related network protocols, and VLSI devices and theory, ASIC design, CPU architecture, PCI, DSP and thesis quality firmware development. Thesis? Good experience in firmware programming in C/C++ under PC DOS, VxWorks and QNX OS.

Some experience in mixed signal CMOS IC circuits design, simulation, layout by Cadence tools. Excited by the challenge. A team work player with creative, self-motivated, cooperative spirit. I have worked in 6 companies and universities in Canada and China in the positions of Senior ASIC Design Engineer, ASIC / FPGA Designer, Lead Hardware Engineer, Hardware Engineer, Firmware Programmer and Research Assistants since I graduated as a MS in abeng essays, Computer Engineering in 1988. These positions carry over 4-year real experience in ASIC/FPGA/VLSI design, and over 6-year real experience in system and hardware board level development, and thesis 10-year systematic theory studies. My background covers Electronics, Microcomputer, Network, Communication, and Control system.

Following are my some ASIC/FPGA hardware and system design experience in real world in order: Vegatron Networks, Toronto, Canada. 2001 Oct 1 - present. Senior ASIC Designer, SoC Architecture Engineer. (Permanent full-time) Development of a System-on-Chip ASIC for a new high-performance switching Router. SystemC, C++, GNU/Visual C++ 6.0, Scripts, High Speed I/O, Verilog, DC, PT, VCS, IP protocols. Developing a high-performance IP routing architecture and interconnection protocol for the 4-million gates ASIC based on multiple IP cores. Cover? Writing a detailed ASIC design specification for RTL design.

Vermax Networks, Ottawa, Canada. May 2001 - Sept 30, 2000. ASIC / FPGA Designer (Permanent full-time) 10GE Egress Traffic Management ASIC Design. Verilog, Vera, Specman, Tcl, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. RSP2 NP, VSC881 Fabric, MPC 8260, PL4, CSIX, PCI32, 10GE, IP, MPLS, ATM, SONET, POS. Developing an ASIC, interfaced to network processor, PL4, H/S interconnect and PCI32. It runs in thesis on oceanarium, three clock domains:700MHz, 200MHz, 33MHZ.

The main clock is 100MHz. Bandwidth is 10gigabit/s. Quality Paper? The main functions include frame error check, traffic policing, traffic shape, traffic meter, interface to MAC and network processors. Thesis On Oceanarium? The project supports 0-15 channels, POS, OC3-192, ATM, MPLS, IP, 1-10 GigaEthernet, voice and cover data traffic. Wrote ASIC specification, defined interfaces and developed chip architecture. Defined and Implemented traffic management algorithms for egress traffic and flow control, Including error check, priority shaping and buffer policing function with optimized structure. Partitioned core-based design and Coded in Verilog at thesis on oceanarium RTL. Designed core-based PCI application interface and wrote testbench for it. Wrote simulation models and performed min. function verification for each block. Wrote simulation models and performed min. function verification for top level with cores. Synthesized with Tcl scripts , and analyzed timing to quality paper fix timing issues at RTL and Gate level.

Implementing first version in the prototyping FPGA: XC2V1000-5 FG456 and back-annotated. Defined software interface and thesis on oceanarium supported firmware designers to cover write ASIC driver. Vermax Networks, Ottawa, Canada. 2000 May - 2001 Sept 30. ASIC / FPGA Designer. (Permanent full-time) OC3 ATM core project: ATM Traffic Executive ASIC Design. DS3 ATM core project: ATM Traffic Executive FPGA Design. Verilog, Vera, DC, PT, Perl, C/C++, Formality, VCS, NCverilog, Undertow, Synplify, Xilinx, VisionICE for MPU 8260, Adtech and thesis on oceanarium Smartbit Traffic Generator, HP Logic Analyzer, Scope.

Deveopled a chip as an ATM traffic scheduler. Fmcg Resume? It works as part of on oceanarium, MMC fabric chipset. Letter? It runs in on oceanarium, two clock domains: 50MHz and 20MHz. Total 512 traffic schedulers are required. Successfully developed, implemented and tested the regression paper, chip in thesis on oceanarium, the Xilinx's XCV1000E version. Analysis? Developed and implemented the dynamical linecard, modem bandwidth allocation and sharing. Implemented 4-level QoS ATM traffic shaping, policing functions in 512 modem schedulers. Implemented traffic congestion control based on modem and on oceanarium subport backpressure signals. Wrote the new version of the ASIC/FPGA design specification, verification and test plan. Developed chip architecture, partitioned, coded in up want when, Verilog at RTL, fixed bugs for all functions.

Wrote model driver and testbench in Verilog and Vera to thesis simulate each new block and top level. Synthesized the ASIC by DC, FPGA by abeng essays, Synplify with constraints and Tcl script files. Used Synopsys 's DC and PT timing analysis for timing debug and timing closure. Wrote test script for VxWorks dshell and VisionICE to test traffic in lab by Adtech, Smartbit. Note: I was awarded Vermax's Gold Pride Award due to dedication to the scheduler chip in 2000. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April.

ATM Simulator FPGA Design Utilizing PCI Bus. VHDL, Synopsys DC, PT, VerilogXL, Viewlogic, Xilinx, C++, PCI32, Logic Analyzer, Scope. Developed an ASIC/FPGA chip for a low cost, high performance ATM simulator to help in on oceanarium, the research and teaching of ATM networks in real world in effects of global warming term papers, cooperation of EE and CS departments. Successfully developed, implemented and thesis tested the ATM chip in the XC4062XLA-09. Developed basic system functions, specifications and architecture for the ATM Simulator. Defined functions of the ATM cell monitor, capture, drop, delay, insertion, error generation. Created a VHDL design flow, partitioned the thesis paper, chip, and coded in VHDL at thesis RTL. Designed an abeng essays, EDIF netlist core based PCI32 backend application interface in VHDL. Thesis On Oceanarium? Wrote model drivers, testbench in VHDL, then simulated each block and abeng essays top level.

Synthesized by Synopsys's Design Compiler. Timing debug and closure by Primetime. Lab test by C++ programs developed to test functions on on oceanarium, a PCI32 FPGA prototyping board. VLSI Lab of ABC, New Brunswick, Canada. 1997 Sept - 2000 April. Some Course Projects in VLSI and Real-time OS. Verilog, Vera, Specman, DC, PT, Formality, VCS, VerilogXL, SignalScan, Synplify, Xilinx. CMOS devices and analysis paper IC analog circuits design and analysis using Cadence Analog Work Bench. CMOS IC digital circuits from RTL to layout using Synopsys and Cadence IC tools. Verilog calculator design synthesized by Synopsys and on oceanarium implementation in abeng essays, Xilinx FPGA. VHDL tutorial: Traffic light system synthesized and simulated by Mentor Quick HDL.

Co-supervised senior thesis: RISC design and implementation in thesis on oceanarium, Xilinx's FPGA. Real-time, multitasking programming in essay up want, C using various semaphores for QNX real-time OS. Diamond Graphics Inc, Ontario, Canada. 1996 Sept - 1997 Aug. Hardware Engineer, FPGA Designer. (Permanent full-time) Development of MCU-based Controller for on oceanarium a graphic scanner.

Synplify, Xilinx FPGA, OrCAD Schematic and PCB, PC DOS and MCU programming in fmcg resume, C. Developed a MCU-based high-accuracy digital controller for a graphic scanner. Developed a new digital control algorithm for on oceanarium a high-accuracy stepper motor. Abeng Essays? Designed a MCU-based prototyping board to thesis demo the letter store, new control algorithm. FPGA design in Xilinx F1.5, and board schematic and PCB design in OrCAD. On Oceanarium? PC DOS programming and MCU 8051 firmware programming in C. Digital Design Center, Wuhan, China.

1994 Sept - 1996 June. Ph.D. Project. Fmcg Resume? Computer-based Non-contact Microsurface Online Measurement. Math algorithms and hardware implementation, DSP, Matlab, OrCAD, MCU 8098 and C firmware. Took part of thesis on oceanarium, a team to develop a Computer Integrated Manufacture System (CIMS).

Developing fast and effects term papers precise online algorithms based on microscope and thesis CCD sensors. Developed a MCU-base prototyping board to demo a new fast and precise online algorithm. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Lead Hardware Engineer, System Engineer. (Permanent full-time) Computer-based Data Acquisition Network System Development.

PC-based Application System design, Digital and Analog Board design, MCU Firmware in C. Developing a specific Remote Data Acquisition and Processing System for customers. Leaded a team to successfully develop some computer-based data acquisition network systems, typically which have over cover letter 1000 points and are over thesis 100Km away from host control room. Successfully developed some MCU-based electronic measure instruments for these projects. Designed system scheme, circuit boards and firmware in multiple, C and on oceanarium debugged in thesis quality paper, labs.

Supports. Teinan Tiger Computer Inc, China. 1988 June - 1994 Aug. Hardware Engineer, Firmware Programmer. (Permanent full-time) An electronic teaching laboratory Development. Schematic and PCB design in on oceanarium, Protel, GAL, PAL, 8051 and firmware in C, DOS programming in C.

Developing an electronic system to be used for multiple regression research paper teaching spoken English. Leaded a team to design, test and install the electronic teaching laboratory for customers. Designed a PC-based host to thesis on oceanarium control an audio network comprised of all 64 audio terminals. Cover? Designed a digital encoder-based mixed-signal circuit board for the 64 audio terminals. Department of Computer Engineering, Wuhan University, China. Developed a Laser-based 2D Intelligent Automatic Measure Coordinator. HeNi Laser device and thesis modulation, stepper motor control, photo-electron sensor, H/W and abeng essays S/W.

Design a transmitter with Laser and a receiver with a coordinator to measure physical displacements. Successfully developed a MPU-controlled automatic measure coordinator with stepper motors. Utilized a modulated Laser beam; Used 8031 MCU to be a controller and programmed in C. Training Courses at Nortel Networks from thesis 2000 to cover 2001. Advanced DC Synthesis Workshop. Synopsys's VERA HVL Workshop High-level Chip Design in Verilog. Verification Strategies in Verilog High-Speed Circuit Design.

Primetime Training Workshop PowerPC 8260 Workshop. Thesis On Oceanarium? Tornado Training Workshop. Master Degree Courses (1997-1999 in EE and CS ) GPA = 87% ( 4.0 / 4.3 ) EE6123 Semiconductor Devices ( CMOS Modeling ) EE4173 Devices and circuits for VLSI ( CMOS IC processing ) EE6133 VLSI Circuits Design ( analog VLSI circuits ) EE6213 ASIC Design ( digital ASIC design ) CS6812 Computer Aided Logic Design ( logic methodology ) CS6845 Computer Networks and Open Systems ( IP Networks ) EE4243 Data Communications ( Modem, Ethernet ) EE4273 Real Time Operation of thesis quality paper, Microcomputers (RT Programming ) EE6373 Signal Processor Architecture EE4543 DSP II ( digital filter design ) CS4815 Advanced Computer Architecture CS5865 Data Networks II.